Hybrid fan-out architecture with EMIB and glass core for heterogeneous die integration applications
Embodiments disclosed herein include electronic packages and methods of forming such packages. In an embodiment, a microelectronic device package may include a redistribution layer (RDL) and an interposer over the RDL. In an embodiment, a glass core may be formed over the RDL and surround the interposer. In an embodiment, the microelectronic device package may further comprise a plurality of dies over the interposer. In an embodiment, the plurality of dies are communicatively coupled with the interposer.
1. A microelectronic device package, comprising:
a redistribution layer (RDL);
an interposer over the RDL;
a mold layer, wherein the interposer is in the mold layer, and wherein the mold layer has an uppermost surface at least as high as an uppermost surface of the interposer;
a glass core over the RDL and surrounding the interposer; and
a plurality of dies over the interposer, wherein the plurality of dies are communicatively coupled with the interposer.
2. The microelectronic device package of claim 1 , further comprising:
conductive vias formed through the glass core.
3. The microelectronic device package of claim 1 , wherein a thickness of the glass core is substantially the same as the thickness of the interposer.
4. The microelectronic device package of claim 1 , wherein the plurality of dies are embedded in the mold layer.
5. The microelectronic device package of claim 1 , wherein the plurality of dies are communicatively coupled to each other by conductive traces in the interposer.
6. The microelectronic device package of claim 1 , wherein the interposer is an active die.
7. The microelectronic device package of claim 6 , wherein the active die comprises active devices at a first process node, and wherein the plurality of dies comprise active devices at a second process node.
8. The microelectronic device package of claim 1 , wherein the interposer is a bridge.
9. The microelectronic device package of claim 1 , further comprising a plurality of interposers, wherein the plurality of interposers are surrounded by the glass core.
10. The microelectronic device package of claim 9 , wherein the plurality of interposers are communicatively coupled to each other by a bridge.
11. The microelectronic device package of claim 10 , wherein the bridge is positioned over a surface of the plurality of interposers that is opposite from the plurality of dies.
12. The microelectronic device package of claim 11 , wherein the bridge is within the RDL.
13. The microelectronic device package of claim 9 , wherein the bridge is an embedded multi-die interconnect bridge (EMIB).
14. The microelectronic device package of claim 1 , wherein a CTE of the glass core matches a CTE of a dielectric layer surrounding the interposer.
15. A method for forming a microelectronic device package, comprising:
attaching a glass core to a glass carrier, wherein the glass carrier comprises a glass substrate, a release film, and a seed layer;
forming a conductive via through the glass core;
disposing an interposer over the glass carrier within the glass core;
disposing a dielectric material over the interposer;
forming a redistribution layer (RDL) over the dielectric layer and the glass core;
detaching the glass carrier; and
mounting a plurality of dies over the interposer, wherein the plurality of dies are communicatively coupled to the interposer.
16. The method of claim 15 , wherein the interposer is an active interposer, wherein the active interposer comprises active devices at a first node, and wherein the plurality of dies comprise active devices at a second node.
17. The method of claim 15 , wherein the glass carrier has a CTE that is substantially equal to the CTE of the interposer.
18. The method of claim 15 , wherein the glass core has a CTE that is substantially equal to the CTE of the dielectric material.
19. The method of claim 15 , further comprising:
disposing a plurality of interposers over the glass carrier within a perimeter of the core.
20. The method of claim 19 , further comprising:
communicatively coupling the plurality of interposers with a bridge.
21. A computing system, comprising:
redistribution layer (RDL);
a glass core over the RDL;
a plurality of first dies within a perimeter of the glass core, wherein the plurality of first dies are communicatively coupled by a bridge, wherein the bridge is in a mold layer, and wherein the mold layer has an uppermost surface at least as high as an uppermost surface of the bridge;
a plurality of second dies over the first dies, wherein the plurality of first dies are communicatively coupled to the first dies; and
a dielectric layer over the first dies and the second dies.
22. The computing system of claim 21 , wherein a CTE of the glass core is substantially equal to a CTE of the dielectric layer.
23. The computing system of claim 21 , wherein the first dies comprise active devices at a first processing node, and wherein the second dies comprise active devices at a second processing node.
24. The computing system of claim 21 , wherein a thickness of the glass core is substantially equal to the thickness of the first dies.