Data Software System Assist
In an embodiment of the invention, an apparatus comprises: a central processing unit (CPU); a volatile memory controller; a non-volatile memory controller; a volatile memory coupled to the volatile memory controller; and a non-volatile memory coupled to the non-volatile memory controller; wherein a ratio of the non-volatile memory to the volatile memory is much less than a typical ratio. In another embodiment of the invention, a method comprises: receiving, by a Central Processing Unit (CPU) receives a command; evaluating, by the CPU, the command; executing, by the CPU, a data software assist to perform the command or activating, by the CPU, a hardware accelerator module to perform the command; and responding, by the CPU, to the command. In yet another embodiment of the invention, an article of manufacture comprises: a non-transitory computer-readable medium having stored thereon instructions operable to permit an apparatus to perform a method comprising: receiving, by a Central Processing Unit (CPU) receives a command; evaluating, by the CPU, the command; executing, by the CPU, a data software assist to perform the command or activating, by the CPU, a hardware accelerator module to perform the command; and responding, by the CPU, to the command.
1 . An apparatus, comprising:
a central processing unit (CPU);
a volatile memory controller;
a non-volatile memory controller;
a volatile memory coupled to the volatile memory controller; and
a non-volatile memory coupled to the non-volatile memory controller;
wherein a ratio of the non-volatile memory to the volatile memory is much less than a typical ratio.
2 . The apparatus of claim 1 , wherein the ratio is less than approximately 500.
3 . The apparatus of claim 1 , wherein the ratio is less than approximately 125.
4 . The apparatus of claim 1 , further comprising:
a data software system assist that is configured to run on the CPU and that is configured to augment at least one data software system.
5 . The apparatus of claim 1 , further comprising:
a hardware accelerator module that is configured to augment at least one data software system.
6 . The apparatus of claim 1 , wherein the CPU is coupled via a link to a host.
7 . The apparatus of claim 1 , wherein the CPU is included in a block and wherein the block performs similar operations as a host.
8 . The apparatus of claim 1 , wherein the CPU executes a data software assist to perform a command.
9 . The apparatus of claim 1 , wherein the CPU activates a hardware accelerator module to perform a command.
10 . The apparatus of claim 1 , wherein during a cache hit, the CPU checks data lookup for a pointer associated with a logical block address (LBA) and sends a content of a cache line associated with the LBA in response to a read LBA request, wherein the pointer points to a cache header and wherein the cache header is associated with a cache line.
11 . The apparatus of claim 1 , wherein during a cache miss, the CPU set up the non-volatile memory controller to send a content in a section in the non-volatile memory to a free cache line associated with a cache header and sends the content in the free cache line in response to a read LBA request.
12 . The apparatus of claim 1 , wherein during a cache miss, the CPU sets up the non-volatile memory controller to send a content in a section in the non-volatile memory to a free cache line associated with a cache header and sends the content in the free cache line in response to a read LBA request and places the cache header at a location in a list depending on a cache eviction policy of the apparatus.
13 . A method, comprising:
receiving, by a Central Processing Unit (CPU) receives a command;
evaluating, by the CPU, the command;
executing, by the CPU, a data software assist to perform the command or activating, by the CPU, a hardware accelerator module to perform the command; and
responding, by the CPU, to the command.
14 . The method of claim 13 , wherein the command comprises a data processing command.
15 . The method of claim 13 wherein the CPU is included in an apparatus and wherein the apparatus comprises a ratio of a non-volatile memory to a volatile memory that is much less than a typical ratio.
16 . The method of claim 15 , wherein the ratio is less than approximately 500.
17 . The method of claim 15 , wherein the ratio is less than approximately 125.
18 . The method of claim 13 , wherein the data software system assist is configured to run on the CPU and that is configured to augment at least one data software system.
19 . The method of claim 13 , wherein the hardware accelerator module is configured to augment at least one data software system.
20 . The method of claim 13 , wherein the CPU is coupled via a link to a host.
21 . The method of claim 13 , wherein the CPU is included in a block and wherein the block performs similar operations as a host.
22 . The method of claim 13 , wherein during a cache hit, the CPU checks data lookup for a pointer associated with a logical block address (LBA) and sends a content of a cache line associated with the LBA in response to a read LBA request, wherein the pointer points to a cache header and wherein the cache header is associated with a cache line.
23 . The method of claim 13 , wherein during a cache miss, the CPU set up the non-volatile memory controller to send a content in a section in the non-volatile memory to a free cache line associated with a cache header and sends the content in the free cache line in response to a read LBA request.
24 . The method of claim 13 , wherein during a cache miss, the CPU sets up the non-volatile memory controller to send a content in a section in the non-volatile memory to a free cache line associated with a cache header and sends the content in the free cache line in response to a read LBA request and places the cache header at a location in a list depending on a cache eviction policy of the apparatus.
25 . An article of manufacture, comprising:
a non-transitory computer-readable medium having stored thereon instructions operable to permit an apparatus to perform a method comprising:
receiving, by a Central Processing Unit (CPU) receives a command;
evaluating, by the CPU, the command;
executing, by the CPU, a data software assist to perform the command or activating, by the CPU, a hardware accelerator module to perform the command; and
responding, by the CPU, to the command.
26 . The article of manufacture of claim 25 , wherein the command comprises a data processing command.
27 . The article of manufacture of claim 25 wherein the CPU is included in the apparatus and wherein the apparatus comprises a ratio of a non-volatile memory to a volatile memory that is much less than a typical ratio.
28 . The article of manufacture of claim 27 , wherein the ratio is less than approximately 500.
29 . The article of manufacture of claim 27 , wherein the ratio is less than approximately 125.
30 . The article of manufacture of claim 25 , wherein the data software system assist is configured to run on the CPU and that is configured to augment at least one data software system.
31 . The article of manufacture of claim 25 , wherein the hardware accelerator module is configured to augment at least one data software system.
32 . The article of manufacture of claim 25 , wherein the CPU is coupled via a link to a host.
33 . The article of manufacture of claim 25 , wherein the CPU is included in a block and wherein the block performs similar operations as a host.
34 . The article of manufacture of claim 25 , wherein during a cache hit, the CPU checks data lookup for a pointer associated with a logical block address (LBA) and sends a content of a cache line associated with the LBA in response to a read LBA request, wherein the pointer points to a cache header and wherein the cache header is associated with a cache line.
35 . The article of manufacture of claim 25 , wherein during a cache miss, the CPU set up the non-volatile memory controller to send a content in a section in the non-volatile memory to a free cache line associated with a cache header and sends the content in the free cache line in response to a read LBA request.
36 . The article of manufacture of claim 15 , wherein during a cache miss, the CPU sets up the non-volatile memory controller to send a content in a section in the non-volatile memory to a free cache line associated with a cache header and sends the content in the free cache line in response to a read LBA request and places the cache header at a location in a list depending on a cache eviction policy of the apparatus.