FPGA functionality mode switch-over
In an embodiment of the invention, an apparatus comprises: a non-volatile memory device; a complex programmable logic device (CPLD) coupled to the non-volatile memory device; a field programmable gate array (FPGA) coupled to the CPLD; and a host coupled to the FPGA; wherein the apparatus triggers a switch of an FPGA image in the FPGA to another FPGA image. In another embodiment of the invention, a method comprises: triggering, by an apparatus, a switch of an FPGA image in a field programmable gate array (FPGA) to another FPGA image; herein the apparatus comprises: a non-volatile memory device; a complex programmable logic device (CPLD) coupled to the non-volatile memory device; the field programmable gate array (FPGA) coupled to the CPLD; and a host coupled to the FPGA. In yet another embodiment of the invention, an article of manufacture comprises a non-transitory computer-readable medium having stored thereon instructions operable to permit an apparatus to perform a method comprising: triggering, by the apparatus, a switch of an FPGA image in a field programmable gate array (FPGA) to another FPGA image, wherein the apparatus comprises: a non-volatile memory device; a complex programmable logic device (CPLD) coupled to the non-volatile memory device; the field programmable gate array (FPGA) coupled to the CPLD; and a host coupled to the FPGA.
1. An apparatus, comprising:
a non-volatile memory device;
a complex programmable logic device (CPLD) coupled to the non-volatile memory device;
a field programmable gate array (FPGA) coupled to the CPLD; and
a host coupled to the FPGA;
wherein the apparatus triggers a switch of an FPGA image in the FPGA to another FPGA image and the FPGA comprises a heartbeat generator that sends a heartbeat signal to the CPLD and stops sending the heartbeat signal if the FPGA image is corrupted.
2. The apparatus of claim 1 , wherein the host triggers the switch from the FPGA image to the another FPGA image.
3. The apparatus of claim 1 , wherein the CPLD selects the another image from the non-volatile memory device and loads the another FPGA image into the FPGA.
4. The apparatus of claim 3 , wherein the CPLD comprises a heartbeat monitor that monitors heartbeat signals.
5. The apparatus of claim 4 , wherein the CPLD loads a default FPGA image into the FPGA in response to the heartbeat monitor failing to detect heartbeat signals.
6. The apparatus of claim 5 , wherein the FPGA sends a report to the host in response to the default FPGA image being loaded into the FPGA and wherein the host switches the default FPGA image in the FPGA to the another FPGA image.
7. The apparatus of claim 3 , wherein the CPLD loads a default FPGA image into the FPGA in response to the FPGA image becoming corrupted.
8. The apparatus of claim 7 , wherein the FPGA sends a report to the host in response to the default FPGA image being loaded into the FPGA and wherein the host switches the default FPGA image in the FPGA to the another FPGA image.
9. The apparatus of claim 1 , wherein the host comprises a heartbeat generator that sends a heartbeat signal to the FPGA, wherein the FPGA comprises a heartbeat pass-through logic for passing the heartbeat signal from the host to the CPLD, and wherein the heartbeat generator stops sending the heartbeat signal if a host connection to the host has failed.
10. A method, comprising:
triggering, by an apparatus, a switch of an FPGA image in a field programmable gate array (FPGA) to another FPGA image;
wherein the apparatus comprises:
a non-volatile memory device;
a complex programmable logic device (CPLD) coupled to the non-volatile memory device;
the field programmable gate array (FPGA) coupled to the CPLD, wherein the FPGA comprises a heartbeat generator that sends a heartbeat signal to the CPLD and stops sending the heartbeat signal if the FPGA image is corrupted; and
a host coupled to the FPGA.
11. The method of claim 10 , wherein the host triggers the switch from the FPGA image to the another FPGA image.
12. The method of claim 10 , wherein the CPLD selects the another image from the non-volatile memory device and loads the another FPGA image into the FPGA.
13. The method of claim 10 , wherein the CPLD comprises a heartbeat monitor that monitors heartbeat signals.
14. The method of claim 13 , wherein the CPLD loads a default FPGA image into the FPGA in response to the FPGA image becoming corrupted.
15. The method of claim 14 , wherein the FPGA sends a report to the host in response to the default FPGA image being loaded into the FPGA and wherein the host switches the default FPGA image in the FPGA to the another FPGA image.
16. The method of claim 14 , wherein the CPLD loads a default FPGA image into the FPGA in response to the heartbeat monitor failing to detect heartbeat signals.
17. The method of claim 16 , wherein the FPGA sends a report to the host in response to the default FPGA image being loaded into the FPGA and wherein the host switches the default FPGA image in the FPGA to the another FPGA image.
18. The method of claim 10 , wherein the host comprises a heartbeat generator that sends a heartbeat signal to the FPGA, wherein the FPGA comprises a heartbeat pass-through logic for passing the heartbeat signal from the host to the CPLD, and wherein the heartbeat generator stops sending the heartbeat signal if a host connection to the host has failed.
19. An article of manufacture, comprising:
a non-transitory computer-readable medium having stored thereon instructions operable to permit an apparatus to perform a method comprising:
triggering, by the apparatus, a switch of an FPGA image in a field programmable gate array (FPGA) to another FPGA image;
wherein the apparatus comprises:
a non-volatile memory device;
a complex programmable logic device (CPLD) coupled to the non-volatile memory device;
the field programmable gate array (FPGA) coupled to the CPLD, wherein the FPGA comprises a heartbeat generator that sends a heartbeat signal to the CPLD and stops sending the heartbeat signal if the FPGA image is corrupted; and
a host coupled to the FPGA.
20. The article of manufacture of claim 19 , wherein the host triggers the switch from the FPGA image to the another FPGA image.
21. The article of manufacture of claim 19 , wherein the CPLD selects the another image from the non-volatile memory device and loads the another FPGA image into the FPGA.
22. The article of manufacture of claim 19 , wherein the CPLD comprises a heartbeat monitor that monitors heartbeat signals.
23. The article of manufacture of claim 22 , wherein the CPLD loads a default FPGA image into the FPGA in response to the heartbeat monitor failing to detect heartbeat signals.
24. The article of manufacture of claim 23 , wherein the FPGA sends a report to the host in response to the default FPGA image being loaded into the FPGA and wherein the host switches the default FPGA image in the FPGA to the another FPGA image.
25. The article of manufacture of claim 19 , wherein the CPLD loads a default FPGA image into the FPGA in response to the FPGA image becoming corrupted.
26. The article of manufacture of claim 25 , wherein the FPGA sends a report to the host in response to the default FPGA image being loaded into the FPGA and wherein the host switches the default FPGA image in the FPGA to the another FPGA image.
27. The article of manufacture of claim 19 , wherein the host comprises a heartbeat generator that sends a heartbeat signal to the FPGA, wherein the FPGA comprises a heartbeat pass-through logic for passing the heartbeat signal from the host to the CPLD, and wherein the heartbeat generator stops sending the heartbeat signal if a host connection to the host has failed.