Devices and methods for improving voltage handling and/or bi-directionality of stacks of elements when connected between terminals

1. An integrated circuit block comprising:

a first node;

a second node;

a series arrangement of one or more capacitors;

a series arrangement of a plurality of switches,

a first compensation capacitor having a first compensation capacitor first terminal and a first compensation capacitor second terminal; and

a second compensation capacitor having a second compensation capacitor first terminal and a second compensation capacitor second terminal;

wherein:

the one or more capacitors are in series with the plurality of switches;

a combination of the one or more capacitors and the plurality of switches is coupled between the first node and the second node;

the plurality of switches are configured to withstand a voltage greater than a voltage withstood by one switch;

the plurality of switches are configured to receive a control signal to enable or disable the switches and thereby adjusting the capacitance between the two nodes,

the first compensation capacitor first terminal is directly connected to a first switch terminal of a first switch of the plurality of switches, and the first compensation capacitor second terminal is directly connected to a second switch terminal of the first switch of the plurality of switches;

the second compensation capacitor first terminal is directly connected to the first switch terminal of the first switch of the plurality of switches, and the second compensation capacitor second terminal is directly connected to a switch terminal of a j-th switch of the plurality of switches; wherein the first compensation capacitor and second compensation capacitor are not connected in parallel across the first switch nor connected in series to each other; and

j is an integer greater or equal to two and less than or equal to a number of switches of the plurality of switches.

2. The integrated circuit block of claim 1 , wherein the plurality of switches comprises:

a set of switches, proceeding from the first switch closest to the first node and farthest from the second node to an n-th switch closest to the second node and farthest from the first node, wherein n is an integer larger than 1.

3. The integrated circuit block of claim 2 , wherein n is smaller or equal to a number of switches of the plurality of switches.

4. The integrated circuit block of claim 2 , wherein:

the one or more compensation capacitors comprise a first set of compensation capacitors and wherein

a first compensation capacitor of the first set of compensation capacitors is located in parallel with the first switch, a second compensation capacitor of the first set of compensation capacitors is located in parallel with a series of the first switch and a second switch, a third compensation capacitor of the first set of compensation capacitors is located in parallel with a series of the first switch, the second switch and a third switch and so on.

5. The integrated circuit block of claim 4 , wherein:

the one or more compensation capacitors further comprise a second set of compensation capacitors and wherein

a first compensation capacitor of the second set of compensation capacitors is located in parallel with the n-th switch, a second compensation capacitor of the second set of compensation capacitors is located in parallel with a series of the n-th switch and an (n−1)-th switch, a third compensation capacitor of the second set of compensation capacitors is located in parallel with a series of the n-th switch, the (n−1)-th switch and an (n−2)-th switch and so on.

6. The integrated circuit block of claim 5 , wherein:

the one or more compensation capacitors and the plurality of switches are integrated on a same chip; and

the one more compensation capacitors physically located on a side of the plurality of switches on the chip.

7. The integrated circuit block of claim 5 , wherein:

the one or more compensation capacitors and the plurality of switches are integrated on a same chip; and

the one or more compensating capacitors are physically located above the plurality of switches on the chip.

8. The integrated circuit block of claim 7 , wherein the plurality of switches comprises FET switches.

9. The integrated circuit block of claim 8 , wherein the one or more compensation capacitors comprise metal-based capacitors.

10. The integrated circuit block of claim 9 , wherein the metal-based capacitors comprise Metal-Metal (MM) capacitors.

11. The integrated circuit block of claim 9 , wherein the metal-based capacitors comprise Metal-Insulator-Metal (MIM) capacitors.

12. The integrated circuit block of claim 4 , wherein: capacitance values of compensation capacitors of the first set of compensation capacitors are monotonically descending from a largest capacitance value of the first compensation capacitor of the first set of compensation capacitors to a lowest capacitance value of a last compensation capacitor of the first set of compensation capacitors.

13. The integrated circuit block of claim 5 , wherein:

capacitance values of the compensation capacitors of the first set of compensation capacitors are monotonically descending from a largest capacitance value of the first compensation capacitor of the first set of compensation capacitors to a lowest capacitance value of a last compensation capacitors of the first set of compensation capacitors; and

capacitance values of the compensation capacitors of the second set of compensation capacitors are monotonically descending from a largest capacitance value of the first compensation capacitor of the second set of compensation capacitors to a lowest capacitance value of a last compensation capacitors of the second set of compensation capacitors.

14. An integrated circuit block comprising:

a first node;

a second node;

a series arrangement of one or more capacitors;

a series arrangement of a plurality of switches comprising:

i) a first set of switches, proceeding from a first switch of the first set of switches closest to the first node and farthest from the second node to an n1-th switch of the first set of switches closest to the second node and farthest from the first node; and

ii) a second set of switches, proceeding from a first switch of the second set of switches closest to the second node and farthest from the first node to an n2-th switch of the second set of switches closest to the first node and farthest to the second node, n1 and n2 being integers larger than 1;

a first compensation capacitor having a first compensation capacitor first terminal and a first compensation capacitor second terminal; and

a second compensation capacitor having a second compensation capacitor first terminal and a second compensation capacitor second terminal; a third compensation capacitor having a third compensation capacitor first terminal and a third compensation capacitor second terminal; wherein:

the one or more capacitors are in series with the plurality of switches;

a combination of the one or more capacitors and the plurality of switches is coupled between the first node and the second node;

the plurality of switches are configured to withstand a voltage greater than a voltage configured to be withstood by one switch;

the plurality of switches are configured to receive a control signal to enable or disable switches of the plurality of switches and thereby adjusting capacitance between the two nodes;

the first compensation capacitor first terminal is directly connected to a first switch terminal of a first switch of the first set of switches, and the first compensation capacitor second terminal is directly connected to a switch terminal consisting of one of i) a second switch terminal of the first switch of the first set of switches or ii) a first switch terminal of an i-th switch of the first set of switches, or iii) a second switch terminal of the i-th switch of the first set of switches; the second compensation capacitor first terminal is directly connected to the first switch terminal of the first switch of the first set of switches, and the second compensation capacitor second terminal is directly connected to a switch terminal of a k-th switch of the first set of switches, wherein the first compensation capacitor and second compensation capacitor are not connected in parallel across the first switch nor connected in series to each other;

the third compensation capacitor first terminal is directly connected to a first switch terminal of a first switch of the second set of switches, and the third compensation capacitor second terminal is directly connected to one of i) a second switch terminal of the first switch of the second set of switches or ii) a first switch terminal of a j-th switch of the second set of switches, or iii) a second switch terminal of the j-th switch of the second set of switches;

i is an integer greater than one and less than or equal to n1; and

j is an integer greater than one and less than or equal to n2.

15. The integrated circuit block of claim 14 , wherein:

proceeding from the first switch of the first set of switches to the n1-th switch of the first set of switches, capacitance values of corresponding compensation capacitors present a sequence of numbers in non-increasing order.

16. The integrated circuit block of claim 15 , wherein:

proceeding from the first switch of the second set of switches to the n2-th switch of the second set of switches, capacitance values of corresponding compensation capacitors present a sequence of numbers in non-increasing order.

17. The integrated circuit block of claim 16 , wherein the plurality of switches comprises FET switches.

18. The integrated circuit block of claim 17 , wherein the compensation capacitors comprise metal-based capacitors.

19. The integrated circuit block of claim 18 , wherein the metal-based capacitors comprise Metal-Metal (MM) capacitors or Metal-Insulator-Metal (MIM) capacitors.

20. A Digitally Tuned Capacitor (DTC) comprising a plurality of the integrated circuit blocks of claim 1 , wherein the plurality of the integrated circuit blocks are configured in parallel.