Semiconductor power device including wire or ribbon bonds over device active region
A semiconductor power device including a base plate; an input lead; an output lead; a field effect transistor (FET) power die disposed over the base plate, wherein the FET power die includes a set of source fingers, a set of drain fingers, and a set of gate fingers disposed directly over an active region, wherein the gate fingers are configured to receive an input signal from the input lead, and wherein the FET power die is configured to process the input signal to generate an output signal at the drain fingers for routing to the output lead; and electrical conductors (wirebonds or ribbons) bonded to the source and/or drain directly over the active region of the FET power die. The electrical conductors produce additional thermal paths between the active region and the base plate for thermal management of the FET power die.
1. A semiconductor power device, comprising:
a base plate;
an input lead;
an output lead;
a semiconductor power die disposed over the base plate, wherein the semiconductor power die is configured to receive an input signal from the input lead and generate an output signal at the output lead, and wherein the semiconductor power die includes metallization disposed over an active region, wherein the semiconductor power die is configured as a field effect transistor (FET) type device, wherein the active region is the channel of the FET type device, wherein the metallization includes a set of source fingers and a set of drain fingers, and wherein the semiconductor power die comprises:
one or more gate bonding pads disposed directly over a non-active-region of the semiconductor power die; and
one or more drain bonding pads disposed directly over the non-active-region of the semiconductor power die; and
a first set of one or more electrical conductors attached to the metallization directly over the active region of the semiconductor power die.
2. The semiconductor power device of claim 1 , wherein the first set of one or more electrical conductors include one or more first ends attached to one or more of the source fingers of the FET type device, respectively.
3. The semiconductor power device of claim 2 , further comprising a metallic bar disposed substantially on the base plate, wherein the first set of one or more electrical conductors include one or more second ends attached to the metallic bar.
4. The semiconductor power device of claim 1 , wherein the first set of one or more electrical conductors include one or more first ends attached to one or more of the drain fingers of the FET type device, respectively.
5. The semiconductor power device of claim 4 , further comprising a bond support including a top metallization layer disposed substantially on the base plate, wherein the first set of one or more electrical conductors include one or more second ends attached to the metallization layer of the bond support.
6. The semiconductor power device of claim 5 , wherein the bond support includes at least one of beryllium oxide (BeO), silicon carbide (SiC), diamond, graphite, or aluminum nitride (AlN).
7. The semiconductor power device of claim 4 , further comprising a capacitor disposed on the base plate, wherein the first set of one or more electrical conductors include one or more second ends attached to a terminal of the capacitor.
8. The semiconductor power device of claim 7 , wherein the capacitor includes a dielectric material comprising at least one of beryllium oxide (BeO), silicon carbide (SiC), diamond, graphite, or aluminum nitride (AlN).
9. The semiconductor power device of claim 1 ,
wherein a first subset of the first set of electrical conductors comprises:
one or more first ends attached to one or more of the source fingers of the FET type device, respectively; and
one or more second ends attached to a metallic bar disposed on the base plate; and
wherein a second subset of the first set of electrical conductors comprises:
one or more first ends attached to one or more of the drain fingers of the FET type device, respectively; and
one or more second ends attached to a bond support or a capacitor disposed on the base plate.
10. The semiconductor power device of claim 1 , further comprising a second set of one or more electrical conductors bonded to the one or more gate bonding pads, respectively, wherein the semiconductor power die is configured to receive the input signal via the second set of one or more electrical conductors.
11. The semiconductor power device of claim 10 , further comprising a capacitor disposed substantially on the base plate, wherein the second set of one or more electrical conductors are attached to a terminal of the capacitor.
12. The semiconductor power device of claim 11 , wherein the capacitor includes a dielectric material comprising at least one of beryllium oxide (BeO), silicon carbide (SiC), diamond, graphite, or aluminum nitride (AlN).
13. The semiconductor power device of claim 1 , further comprising a second set of one or more electrical conductors attached to the one or more drain bonding pads, respectively, wherein the output signal is configured to be routed to the output lead via the second set of one or more electrical conductors.
14. The semiconductor power device of claim 1 , wherein the semiconductor power die further comprises one or more source bonding pads disposed directly over the non-active-region of the semiconductor power die.
15. The semiconductor power device of claim 14 , further comprising a second set of one or more electrical conductors attached to the one or more source bonding pads, respectively, wherein the second set of one or more electrical conductors are electrically coupled to the base plate.
16. A semiconductor power device, comprising:
a base plate;
an input lead;
an output lead;
a semiconductor power die disposed over the base plate, wherein the semiconductor power die is configured to receive an input signal from the input lead and generate an output signal at the output lead, wherein the semiconductor power die includes metallization disposed over an active region, wherein the semiconductor power die is configured as a field effect transistor (FET) type device, wherein the active region is the channel of the FET type device, and wherein the metallization includes a set of source fingers and a set of drain fingers, and wherein the semiconductor power die comprises one or more metalized via holes electrically coupling the one or more source fingers to the base plate; and
a set of one or more electrical conductors attached to the metallization directly over the active region of the semiconductor power die.
17. The semiconductor power device of claim 1 , wherein the channel includes a set of separate channels of the FET type device, and wherein the set of source fingers and the set of drain fingers disposed are directly over the separate channels, respectively.
18. A semiconductor power device, comprising:
a base plate;
an input lead;
an output lead;
a field effect transistor (FET) power die disposed over the base plate, wherein the FET power die includes a set of source fingers, a set of drain fingers, and a set of gate fingers disposed directly over an active region, wherein the set of gate fingers is configured to receive an input signal from the input lead, and wherein the FET power die is configured to process the input signal to generate an output signal at the set of drain fingers for routing to the output lead, and wherein the FET comprises:
one or more gate bonding pads disposed directly over a non-active-region of the FET; and
one or more drain bonding pads disposed directly over the non-active-region of the FET; and
a set of one or more electrical conductors attached to at least one of the set of source fingers or the set of drain fingers directly over the active region of the FET power die.
19. The semiconductor power device of claim 18 , wherein the FET power die is configured as a gallium-nitride (GaN) on silicon carbide (SiC) high electron mobility transistor (HEMT).