IP Library Granted Patent US 10,291,120
Granted Patent B2
US 10,291,120 · App. 16/028,202 · Granted May 14, 2019

Boost DC-DC converter having digital control and reference PWM generators

Inventor: Hassan Ihs (San Diego, CA)
Assignee: Chaoyang Semiconductor Jiangyin Technology Co., Ltd.
H02M3/157H02M3/156H02M3/158H02M3/1588H02M2001/0025H02M2003/1566Y02B70/1466
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Quick Facts
Patent No.
US 10,291,120
App. No.
16/028,202
Granted
May 14, 2019
Kind
B2
Abstract

A boost DC-DC converter operating in pulse frequency modulation (PFM) and pulse width modulation (PWM) modes includes a plurality of PWM signal generators. The PWM signal generators generate PWM signals with different duty cycles. PWM signals with larger duty cycles may be selected for use in undervoltage situations.

Claims (15)

1. A method of controlling a switching boost DC-DC converter, comprising:

boosting, by an input inductor, an input voltage provided by a power supply source;

providing, by the input inductor, to an output capacitor a boosted voltage;

providing, by the output capacitor, an output voltage of the switching boost DC-DC converter based on the boosted voltage;

producing, by a first pulse width modulation (PWM) signal generator, a first PWM signal having a first duty cycle;

producing, by a second PWM signal generator, a second PWM signal having a second duty cycle, the second duty cycle having a higher duration than the first duty cycle;

determining that the output voltage of the switching boost DC-DC converter is below a first predefined voltage level, wherein the first predefined voltage level is a desired boost DC-DC converter output voltage minus a first voltage tolerance;

controlling, by a logic circuitry, states of a high side switch and a low side switch of the switching boost DC-DC converter based on the first PWM signal in response to determining that the output voltage of the switching boost DC-DC converter is below the first predefined voltage level; and

determining that the output voltage of the switching boost DC-DC converter is above the first predefined voltage level;

controlling, by the logic circuitry the states of the high switch and the low side switch of the switching boost DC-DC converter based on the second PWM signal in response to determining that the output voltage of the switching boost DC-DC converter is above the first predefined voltage level;

wherein the high side switch and the low side switch are coupled in series, with a node between the high side switch and the low side switch coupling to the input inductor of the switching boost DC-DC converter, wherein the input inductor has a first terminal coupling to the power supply source and a second terminal coupling to the node between the high side switch and the low side switch; and

further comprising coupling the first terminal of the input inductor and the second terminal of the input inductor of the switching boost DC-DC converter if the output voltage of the switching boost DC-DC converter is above a second predefined voltage level, wherein the second predefined voltage level is a sum of the desired boost DC-DC converter output voltage and a second voltage tolerance; and

further comprising deactivating the high side switch and the low side switch if the output voltage of the switching boost DC-DC converter is above the second predefined voltage level.

2. The method of claim 1 , wherein the boosting, by the input inductor, the input voltage provided by the power supply source occurs when the low side switch is active.

3. The method of claim 1 , wherein the providing, by the input inductor, to the output capacitor the boosted voltage occurs when the high side switch is active.

Assignments (6)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 24, 2023
From: CHAOYANG SEMICONDUCTOR (SHANGHAI) CO., LTD.
To: ENDURA IP HOLDINGS LTD.
Reel/Frame 063424/0226 →
CHANGE OF NAME Recorded Mar 29, 2022
From: CHAOYANG SEMICONDUCTOR JIANGYIN TECHNOLOGY CO., LTD.
To: CHAOYANG SEMICONDUCTOR (SHANGHAI) CO., LTD
Reel/Frame 061088/0212 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 1, 2018
From: ENDURA TECHNOLOGIES LLC
To: ENDURA IP HOLDINGS LTD.
Reel/Frame 046529/0797 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 1, 2018
From: ENDURTECH (HONG KONG) LIMITED
To: CHAOYANG SEMICONDUCTOR JIANGYIN TECHNOLOGY CO., LTD.
Reel/Frame 046529/0826 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 1, 2018
From: IHS, HASSAN
To: ENDURA TECHNOLOGIES LLC
Reel/Frame 046711/0110 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 1, 2018
From: ENDURA IP HOLDINGS LTD.
To: ENDURTECH (HONG KONG) LIMITED
Reel/Frame 046711/0164 →
Continuity (3)
Continuation 15376143 · Dec 12, 2016
Provisional Application 62266186 · Dec 11, 2015
Related Publication 20180316265A1 · Nov 1, 2018