Clock doublers with duty cycle correction
A system for correcting a duty cycle comprises a digital quadrature generator circuit, a frequency doubler circuit, a first duty cycle correction circuit coupled between the digital quadrature generator circuit and the frequency doubler circuit, and a second duty cycle correction circuit coupled between the digital quadrature generator circuit and the frequency doubler circuit. The first duty cycle correction circuit comprises a first stacked duty cycle correction circuit and the second duty cycle correction circuit comprises a second stacked duty cycle correction circuit.
1. An apparatus for correcting a duty cycle, comprising:
a first transistor of a first conductivity type having a first drain, a first source, and a first gate;
a second transistor of the first conductivity type in series with the first transistor, and having a second drain, a second source, and a second gate;
a third transistor of a second conductivity type having a third drain, a third source, and a third gate;
a fourth transistor of the second conductivity type in series with the third transistor, and having a fourth drain, a fourth source, and a fourth gate;
an input node coupled to the first gate and the third gate, wherein the input node is configured to receive an input clock signal with a first duty cycle;
an output node directly coupled to the second drain and the fourth drain and indirectly coupled to the first drain or the third drain, wherein the output node is configured to generate an output clock signal with a second duty cycle;
a gate node coupled to the second gate and the fourth gate;
a positive voltage supply coupled to a current terminal of the first transistor;
a ground terminal coupled to a current terminal of the third transistor; and
a resistor directly coupled to the output node and directly coupled to the gate node.
2. The apparatus of claim 1 , wherein the input clock signal is configured to selectively control a pull up drain current through the second transistor and to selectively control a pull down drain current through the fourth transistor.
3. The apparatus of claim 1 , wherein the input clock signal is configured to selectively switch ON the first transistor and the third transistor and to selectively switch OFF the first transistor and the third transistor.
4. The apparatus of claim 1 , wherein the second duty cycle of the output clock signal is higher than the first duty cycle of the input clock signal when the first duty cycle is less than a 50 percent duty cycle clock signal.
5. The apparatus of claim 4 , wherein the second duty cycle of the output clock signal is lower than the first duty cycle of the input clock signal when the first duty cycle is greater than the 50 percent duty cycle clock signal.
6. The apparatus of claim 1 , including an inverter coupled to the output node, wherein the inverter is configured to invert the output clock signal.
7. The apparatus of claim 1 , wherein the fourth transistor is configured to generate a pull down drain current that is larger than a pull up drain current of the second transistor when the first duty cycle is less than a 50 percent duty cycle.
8. The apparatus of claim 1 , wherein the second transistor is configured to generate a pull up drain current that is larger than a pull down drain current of the fourth transistor when the first duty cycle is greater than a 50 percent duty cycle.