Successive approximation register (SAR) analog to digital converter (ADC) with overlapping reference voltage ranges
An analog to digital converter (ADC) is disclosed. The ADC includes a DAC which generates a first signal based on an analog input and a digital input word, and a comparator which generates a comparator output having a value corresponding with a sign of a difference between first and second signals. During a first time period, the second signal is equal to a reference signal, the first signal is equal to an analog input, and the comparator generates a first comparator output. During a second time period, the second signal is equal to the reference signal, the first signal is equal to a the analog input plus a predetermined signal, and the comparator generates a second comparator output. A SAR logic circuit generates the digital input word for the DAC based on the first and second comparator outputs.
1. A successive approximation register (SAR) analog to digital converter (ADC), comprising:
a SAR logic circuit configured to generate a digital input word;
a DAC, configured to receive the digital input word and an analog input, and to generate a first signal based on the analog input and the digital input word; and
a comparator, comprising:
a first input terminal configured to receive the first signal, and
a second input terminal configured to receive a second signal,
wherein the comparator is configured to generate a comparator output based on the first and second signals, wherein the comparator output has a value corresponding with a sign of a difference between the first and second signals,
wherein, during a first time period, the second signal is equal to a reference signal, the first signal is equal to the analog input, and the comparator is configured to generate a first comparator output based on the first and second signals of the first time period, and
wherein, during a second time period, the second signal is equal to the reference signal, the first signal is equal to the analog input plus a predetermined voltage, and the comparator is configured to generate a second comparator output based on the first and second signals of the second time period,
wherein the SAR logic circuit is further configured to receive the first and second comparator outputs, and to generate the digital input word for the DAC based on the first and second comparator outputs.
2. The SAR ADC of claim 1 , wherein the SAR logic is configured to generate a digital output word corresponding with the analog input, and to determine an MSB of the digital output word based on the first comparator output.
3. The SAR ADC of claim 1 , wherein the SAR logic is configured to generate a digital representation of the analog input based on the first and second comparator outputs.
4. The SAR ADC of claim 1 ,
wherein, during a third time period, the second signal is equal to the reference signal, and the first signal is equal to the analog input plus the predetermined voltage plus a step,
wherein the sign of the step is determined by the SAR logic based on the second comparator output, and
wherein the comparator is configured to generate a third comparator output based on the first and second signals of the third time period.
5. The SAR ADC of claim 4 , wherein the SAR logic is configured to generate a digital representation of the analog input based on the first, second, and third comparator outputs.
6. The SAR ADC of claim 1 , wherein the DAC comprises a plurality of capacitors and a plurality of switches, wherein each of the switches is connected to a particular one of the capacitors, is selectively connected to either of a ground voltage and a reference voltage, and is configured to selectively connect the particular capacitor to either of the ground voltage and the reference voltage.
7. The SAR ADC of claim 6 , wherein, during the second time period, the SAR logic is configured to cause the DAC to generate the first signal such that the first signal is equal to a voltage of the analog input plus the predetermined voltage, wherein, in response to the first comparator output indicating that the analog input is less than the reference signal, while the first signal is generated, one or more of the switches of the DAC are switched from being connected to the ground voltage to being connected to the reference voltage.
8. The SAR ADC of claim 7 , wherein the one or more switches correspond with the particular capacitors of the DAC which, in response to the one or more switches being switched, cause a voltage of the first signal to increase by the predetermined voltage.
9. The SAR ADC of claim 6 , wherein, during the second time period, the SAR logic is configured to cause the DAC to generate the first signal such that the first signal is equal to a voltage of the analog input minus the predetermined voltage, wherein, in response to the first comparator output indicating that the analog input is greater than the reference signal, while the first signal is generated, one or more of the switches of the DAC are switched from being connected to the reference voltage to being connected to the ground voltage.
10. The SAR ADC of claim 9 , wherein the one or more switches correspond with the particular capacitors of the DAC which, in response to the one or more switches being switched, cause a voltage of the first signal to decrease by the predetermined voltage.
11. A method of using a successive approximation register (SAR) analog to digital converter (ADC) to determine a digital output word having a value corresponding with a value of an analog input, the method comprising:
with an SAR logic circuit of the SAR ADC, generating a digital input word;
with a DAC of the SAR ADC:
receiving the digital input word and the analog input, and
generating a first signal based on the analog input and the digital input word;
with a comparator of the SAR ADC:
receiving the first signal at a first input terminal,
receiving a second signal at a second input terminal, and
generating a comparator output based on the first and second signals, wherein the comparator output has a value corresponding with a sign of a difference between the first and second signals,
wherein, during a first time period, the second signal is equal to a reference signal, the first signal is equal to the analog input, and the comparator is configured to generate a first comparator output based on the first and second signals of the first time period, and
wherein, during a second time period, the second signal is equal to the reference signal, the first signal is equal to the analog input plus a predetermined voltage, and the comparator is configured to generate a second comparator output based on the first and second signals of the second time period; and
with the SAR logic circuit of the SAR ADC:
receiving the first and second comparator outputs, and
generating the digital input word for the DAC based on the first and second comparator outputs.
12. The method of claim 11 , further comprising, with the SAR logic, determining an MSB of the digital output word based on the first comparator output.
13. The method of claim 11 , further comprising, with the SAR logic, generating a digital representation of the analog input based on the first and second comparator outputs.
14. The method of claim 11 ,
wherein, during a third time period, the second signal is equal to the reference signal, and the first signal is equal to the analog input plus the predetermined voltage plus a step,
wherein the sign of the step is determined by the SAR logic based on the second comparator output, and
wherein the method further comprises, with the comparator, generating a third comparator output based on the first and second signals of the third time period.
15. The method of claim 14 , further comprising, with the SAR logic, generating a digital representation of the analog input based on the first, second, and third comparator outputs.
16. The method of claim 11 , wherein the DAC comprises a plurality of capacitors and a plurality of switches, wherein each of the switches is connected to a particular one of the capacitors, and is selectively connected to either of a ground voltage and a reference voltage, and wherein the method further comprises, with the switches, connecting each particular capacitor to either of the ground voltage and the reference voltage.
17. The method of claim 16 , further comprising, during the second time period, with the SAR logic:
causing the DAC to generate the first signal such that the first signal is equal to a voltage of the analog input plus the predetermined voltage, and,
in response to the first comparator output indicating that the analog input is less than the reference signal, while the first signal is generated, switching one or more of the switches of the DAC from being connected to the ground voltage to being connected to the reference voltage.
18. The method of claim 17 , wherein the one or more switches correspond with the particular capacitors of the DAC which, in response to the one or more switches being switched, cause a voltage of the first signal to increase by the predetermined voltage.
19. The method of claim 16 , further comprising, during the second time period, with the SAR logic:
causing the DAC to generate the first signal such that the first signal is equal to a voltage of the analog input minus the predetermined voltage, and,
in response to the first comparator output indicating that the analog input is greater than the reference signal, while the first signal is generated, switching one or more of the switches of the DAC from being connected to the reference voltage to being connected to the ground voltage.
20. The method of claim 19 , wherein the one or more switches correspond with the particular capacitors of the DAC which, in response to the one or more switches being switched, cause a voltage of the first signal to decrease by the predetermined voltage.