IP Library Granted Patent US 10,699,989
Granted Patent B2
US 10,699,989 · App. 16/031,948 · Granted Jun 30, 2020

Semiconductor package with grounding device and related methods

Inventors: Atapol Prajuckamol (Klaeng, TH); Sw Wang (Seremban, MY); Kai Chat Tan (Tangkak, MY)
Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
H01L23/4951H01L23/4952H01L23/49861H01L24/03H01L2224/16245H01L2224/40247H01L2224/48091H01L2224/48247H01L2224/48465H01L2224/73265H01L2224/81192H01L2224/83385H01L2224/92247
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Quick Facts
Patent No.
US 10,699,989
App. No.
16/031,948
Granted
Jun 30, 2020
Kind
B2
Abstract

Implementations of a semiconductor package may include a first side of a die coupled to a first side of an electrically insulative layer, a second side of the electrically insulative layer coupled to a lead frame, and at least one ground stud physically coupled to the lead frame and to the die, the at least one ground stud extending from the second side of the electrically insulative layer into the electrically insulative layer from the lead frame. The die may be wire bonded to the lead frame.

Claims (20)

1. A semiconductor package comprising:

a die coupled to a lead frame, the die comprising an electrically insulative layer; and

at least one ground stud physically coupled to the lead frame and to the die, the at least one ground stud extending from the lead frame towards the die;

wherein the electrically insulative layer is a wafer backside coating.

2. The package of claim 1 , wherein the electrically insulative layer is coupled between the lead frame and the die.

3. The package of claim 1 , wherein the at least one ground stud comprises two ground studs physically coupled to the lead frame and the die.

4. The package of claim 2 , wherein the at least one ground stud extends into the electrically insulative layer.

5. The package of claim 2 , wherein the lead frame comprises a die flag coupled to a second side of the electrically insulative layer.

6. The package of claim 5 , wherein the at least one ground stud physically contacts the die flag and is physically coupled to the die.

7. The package of claim 1 , wherein the semiconductor package is a chip on lead package.

8. A semiconductor package comprising:

a die coupled to an electrically non-conductive layer;

a lead frame coupled to the electrically non-conductive layer, the electrically non-conductive layer coupled between the die and the lead frame; and

at least one ground stud coupled to the lead frame and the die;

wherein the electrically non-conductive layer is a wafer backside coating.

9. The package of claim 8 , wherein the at least one ground stud comprises two ground studs physically coupled to the lead frame and the die.

10. The package of claim 8 , wherein the at least one ground stud extends into the electrically non-conductive layer.

11. The package of claim 8 , wherein the at least one ground stud is 35-40 micrometers thick.

12. The package of claim 8 , wherein the lead frame comprises a die flag coupled to the electrically non-conductive layer.

13. The package of claim 12 , wherein the at least one ground stud physically contacts the die flag and is physically coupled to the die.

Assignments (3)
RELEASE OF SECURITY INTEREST IN PATENTS RECORDED AT REEL 047399, FRAME 0631 Recorded Jun 23, 2023
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 064078/0001 →
SECURITY INTEREST Recorded Nov 1, 2018
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 047399/0631 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 10, 2018
From: PRAJUCKAMOL, ATAPOL; WANG, SW; TAN, KAI CHAT
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 046312/0013 →
Continuity (2)
Continuation 15789120 · Oct 20, 2017
Related Publication 20190122963A1 · Apr 25, 2019