Dynamic microprocessor gate design tool for area/timing margin control

1. A computer-implemented method for optimizing microprocessor gates in a microprocessor comprising:

receiving, via a processor, a dataset comprising a model of a plurality of gates of a microprocessor on a chip;

applying to the model, via the processor, a proposed gate change to a physical size of one or more of the plurality of gates, wherein the proposed gate change results in a signal transmission time less than a predetermined threshold time;

evaluating, via the processor, an area degradation value indicative of an occupation of physical space on the chip by the gates on the microprocessor based on the proposed gate change;

determining, via the processor, a margin value based on the signal transmission time and the area degradation value, the margin value is a weighted comparison of the signal transmission time and the area degradation value;

modifying, via the processor, the dataset to include the proposed gate change; and

outputting a modified dataset that is used to fabricate the chip with the microprocessor that comprises the plurality of gates with the changed physical sizes.

2. The computer-implemented method of claim 1 , further comprising: determining whether the model would result a signal transmission time less than a predetermined threshold time by comparing the margin value to a predetermined margin target.

3. The computer-implemented method of claim 2 , wherein the predetermined margin target is higher when a sector of the microprocessor is identified as timing critical.

4. The computer-implemented method of claim 2 , wherein the predetermined margin target is lower when a sector of the microprocessor is identified as not timing critical.

5. The computer-implemented method of claim 2 , further comprising:

scaling, via the processor, the predetermined margin target based on the margin value exceeding a predetermined improvement threshold.

6. The computer-implemented method of claim 1 , wherein determining the margin value comprises:

receiving, via the processor, a weight factor indicative of a relative criticality of at least one sector of the microprocessor with respect to one or more of signal transmission time and area degradation;

identifying, via the processor, a gate sector indicative of a portion of the microprocessor affected by the proposed gate change; and

weighting the margin value with the weight factor based on the gate sector.

7. A system for optimizing microprocessor gates in a microprocessor comprising:

a processor configured to:

receive a dataset comprising a model of a plurality of gates of a microprocessor on a chip;

apply to the model a proposed gate change to one or more of the plurality of gates, the proposed gate change transforming sizes of one or more gates on a chip, and wherein the proposed gate change results in a signal transmission time less than a predetermined threshold time;

evaluate an area degradation value based on the proposed gate change, the area degradation value indicative of physical space on the chip that is occupied by the gates;

determine a margin value based on the signal transmission time and the area degradation value, the margin value is a weighted comparison of the signal transmission time and the area degradation value;

modify the dataset to include the proposed gate change; and

output a modified dataset for fabricating the microprocessor comprising the one or more gates with the transformed sizes.

8. The system of claim 7 , wherein the proposed gate change comprises a change in a transmission line in the model, and processor is configured to determine whether the transmission line, if implemented in a physical circuit, would result in a signal transmission time less than a predetermined threshold time by comparing the margin value to a predetermined margin target.

9. The system of claim 8 , wherein the predetermined margin target is higher when a sector of the microprocessor is identified as timing critical.

10. The system of claim 8 , wherein the predetermined margin target is lower when a sector of the microprocessor is identified as not timing critical.

11. The system of claim 8 , wherein the processor is further configured to:

scale the predetermined margin target based on the margin value exceeding a predetermined improvement threshold.

12. The system of claim 7 , wherein the processor is configured to:

receive a weight factor indicative of a relative criticality of at least one sector of the microprocessor with respect to one or more of signal transmission time and area degradation;

identify a gate sector indicative of a portion of the microprocessor affected by the proposed gate change; and

determine the margin value by weighting the margin value with the weight factor based on the gate sector.

13. A non-transitory computer readable storage medium having program instructions embodied therewith for optimizing microprocessor gates in a microprocessor, the program instructions executable by a processor to cause the processor to perform a method comprising:

receiving a dataset comprising a model of a plurality of gates of a microprocessor on a chip;

applying to the model a proposed gate change to a physical size of one or more of the plurality of gates, wherein the proposed gate change results in a signal transmission time less than a predetermined threshold time;

evaluating an area degradation value indicative of physical space on the chip that is occupied by the gates of the microprocessor based on the proposed gate change;

determining a margin value based on the signal transmission time and the area degradation value, the margin value is a weighted comparison of the signal transmission time and the area degradation value;

modifying the dataset to include the proposed gate change; and

outputting a modified dataset that is used to fabricate the chip with the microprocessor that comprises the plurality of gates with the changed physical sizes.

14. The computer readable storage medium of claim 13 , wherein the method further comprises determining whether a transmission line in the model, if implemented in a physical circuit, would result a signal transmission time less than a predetermined threshold time by comparing the margin value to a predetermined margin target.

15. The computer readable storage medium of claim 14 , wherein the predetermined margin target is higher when a sector of the microprocessor is identified as timing critical.

16. The computer readable storage medium claim 14 , wherein the predetermined margin target is lower when a sector of the microprocessor is identified as not timing critical.

17. The computer readable storage medium of claim 14 , further comprising:

scaling, via the processor, the predetermined margin target based on the margin value exceeding a predetermined improvement threshold.

18. The computer readable storage medium of claim 13 , wherein determining the margin value comprises:

receiving, via the processor, a weight factor indicative of a relative criticality of at least one sector of the microprocessor with respect to one or more of signal transmission time and area degradation;

identifying, via the processor, a gate sector indicative of a portion of the microprocessor affected by the proposed gate change; and

weighting the margin value with the weight factor based on the gate sector.