Integrating a junction field effect transistor into a vertical field effect transistor
Embodiments of the invention include first and second devices formed on a substrate. The first device includes a bottom source or drain (S/D) region, a plurality of fins formed on portions of the bottom S/D region, a bottom spacer formed on the bottom S/D region, a dielectric layer, a gate, a top S/D region formed on each fin of a plurality of fins, and one or more contacts. The dielectric layer is disposed between the gate and the fin of the plurality of fins. The second device includes a bottom doped region, a channel formed the bottom doped region, a sidewall doped region of the channel, a gate coupled to the sidewall doped region, a top doped region, and one or more contacts. A junction is formed between the channel and the sidewall doped region. The cap layer is formed on the gate and the top doped region.
1. A method of fabricating semiconductor devices, the method comprising:
performing fabrication operations to form a first transistor device on a substrate, wherein the fabrication operations to form the first transistor device comprise:
forming one or more fins on the substrate;
forming a bottom source or drain (S/D) region on the substrate;
forming a bottom spacer on the bottom S/D region;
forming a dielectric layer over the one or more fins;
forming a metal gate for the one or more fins over the dielectric layer;
forming a cap layer over the bottom spacer and metal gate; and
forming a top S/D region over the one or more fins; and
performing fabrication operations to form a second transistor device on the substrate, wherein the fabrication operations to form the second transistor device comprise:
forming a bottom region of the second transistor device on the substrate;
forming the channel region on the bottom region, wherein the one or more fins of the first transistor device are formed with the channel region of the second transistor device;
forming the bottom spacer;
forming sidewalls of the channel region of the second transistor device;
forming a metal gate for the second transistor device, wherein the metal gate for the second transistor device is formed with the metal gate for the one or more fins;
forming the cap layer over bottom spacer and the metal gate of the second transistor device;
forming the top region over the sidewalls and the channel region; and
forming one or more contacts over the top region.
2. The method of claim 1 , wherein the first transistor device comprises a vertical fin field effect transistor (VFET) and the second transistor device comprises a junction field effect transistor (JEFT).
3. The method of claim 1 , wherein the gate of the first semiconductor device and the second semiconductor device is a wrap-around gate.
4. The method of claim 1 , wherein the dielectric layer comprises a high-k dielectric layer.
5. The method of claim 1 , wherein there is no high-k dielectric layer on the JFET gate.
6. The method of claim 1 , wherein a width dimension of the channel region is greater that a width dimension of each of the one or more fins.
7. The method of claim 1 , wherein forming the one or more fins comprises a self-aligned double patterning (SADP) process.
8. The method of claim 1 , wherein forming the channel region of the second transistor comprises a direct lithography process.
9. The method of claim 1 further comprising forming one or more shallow trench isolation layers between the first transistor device and the second transistor device.
10. The method of claim 1 , wherein:
the channel comprises sidewalls and a main body region; and
the sidewalls of the channel comprise a different type of material than the main body region of the channel.