Three-dimensional nonvolatile memory and related read method designed to reduce read disturbance
A nonvolatile memory device performs a read operation comprising first and second intervals. In the first interval the device applies a turn-on voltage to string selection lines and ground selection lines connected to the string selection transistors and the ground selection transistors, respectively. In the second interval, the device applies a turn-off voltage to unselected string selection lines and unselected ground selection lines while continuing to apply the turn-on voltage to a selected string selection line and a selected ground selection line. In both the first and second intervals, the device applies a first read voltage to a selected wordline connected to memory cells to be read by the read operation and applying a second read voltage to unselected wordlines among connected to memory cells not to be read by the read operation.
1. A three-dimensional (3D) flash memory device comprising:
a plurality of cell strings, each of the plurality of cell strings including a string select transistor, a plurality of memory cells and a ground select transistor stacked in a direction perpendicular to a substrate; and
a decoder configured to, during a read operation, apply a first turn-on voltage to a selected string selection line among a plurality of string selection lines connected to a plurality of string selection transistors of the plurality of cell strings, apply a second turn-on voltage and a third turn on voltage to a first unselected string selection line and a second unselected string selection line respectively among the plurality of string selection lines,
wherein the decoder is further configured to, during the read operation, apply a fourth turn-on voltage to a selected ground selection line among a plurality of ground selection lines connected to a plurality of ground selection transistors of the plurality of cell strings,
after applying the first through fourth turn-on voltages, during the read operation, the decoder is further configured to adjust a first voltage of the first unselected string selection line to a first level,
after adjusting the first voltage of the first unselected string selection line, during the read operation, the decoder is further configured to adjust a second voltage of the second unselected string selection line to a second level, and
string selection transistors, among the plurality of string selection transistors, connected to the selected string selection line and ground selection transistors, among the plurality of ground selection transistors, connected to the selected ground selection line are turned-on while the first voltage and the second voltage are adjusted.
2. The 3D flash memory device of claim 1 , wherein the first level is identical with the second level.
3. The 3D flash memory device of claim 1 , wherein the first voltage having the first level turns-off string selection transistors, among the plurality of string selection transistors, connected to the first unselected string selection lines.
4. The 3D flash memory device of claim 1 , wherein the second voltage having the second level turns-off string selection transistors, among the plurality of string selection transistors, connected to the second unselected string selection lines.
5. The 3D flash memory device of claim 1 , wherein ground selection transistors, among the plurality of ground selection transistors, corresponding to the selected string selection line and the second unselected string selection line are connected to a same ground selection line among the plurality of ground selection lines.
6. The 3D flash memory device of claim 1 , wherein the plurality of memory cells of each of the plurality of cell strings are connected to the decoder through a plurality of word lines, and
the decoder is further configured to, during the read operation, apply a first read voltage to a selected word line and apply a second read voltage to a unselected word line among the plurality of word lines.
7. The 3D flash memory device of claim 6 , wherein the second read voltage turns-on a memory cell among the plurality of memory cells of each of the plurality of cell strings.
8. The 3D flash memory device of claim 1 , further comprising:
a page buffer connected to the plurality of cell strings through a bit line and configured to, during the read operation, sense a voltage of the bit line.
9. A method of performing a read operation of a three-dimensional (3D) flash memory device, the 3D flash memory device comprising a plurality of cell strings, each of the plurality of cell strings including a string select transistor, a plurality of memory cells and a ground select transistor stacked in a direction perpendicular to a substrate, the method comprising:
applying a first turn-on voltage to a selected string selection line among a plurality of string selection lines connected to a plurality of string selection transistors of the plurality of cell strings;
applying a second turn-on voltage and a third turn on voltage to a first unselected string selection line and a second unselected string selection line respectively among the plurality of string selection lines;
applying a fourth turn-on voltage to a selected ground selection line among a plurality of ground selection lines connected to a plurality of ground selection transistors of the plurality of cell strings;
after applying the first through fourth turn-on voltages, adjusting a first voltage of the first unselected string selection line to a first level; and
after adjusting the first voltage of the first unselected string selection line, adjusting a second voltage of the second unselected string selection line to a second level,
wherein string selection transistors, among the plurality of string selection transistors, connected to the selected string selection line and ground selection transistors, among the plurality of ground selection transistors, connected to the selected ground selection line are turned-on while the first voltage and the second voltage are adjusted.
10. The method of claim 9 , wherein the first level is identical with the second level.
11. The method of claim 9 , wherein the first voltage having the first level turns-off string selection transistors, among the plurality of string selection transistors, connected to the first unselected string selection lines.
12. The method of claim 9 , wherein the second voltage having the second level turns-off string selection transistors, among the plurality of string selection transistors, connected to the second unselected string selection lines.
13. The method of claim 9 , wherein ground selection transistors, among the plurality of ground selection transistors, corresponding to the selected string selection line and the second unselected string selection line are connected to a same ground selection line among the plurality of ground selection lines.
14. The method of claim 9 , further comprising:
applying a first read voltage to a selected word line among a plurality of word lines connected to the plurality of memory cells of each of the plurality of cell strings; and
applying a second read voltage to a unselected word line among the plurality of word lines.
15. The method of claim 14 , wherein the second read voltage turns-on a memory cell among the plurality of memory cells of each of the plurality of cell strings.
16. A storage device comprising:
a controller configured to transmit a read command and an address; and
a three-dimensional (3D) flash memory device comprising a plurality of memory blocks, each of the plurality of memory blocks including a plurality of cell strings, each of the plurality of cell strings including a string select transistor, a plurality of memory cells and a ground select transistor stacked in a direction perpendicular to a substrate; and
a decoder configured to, in response to the read command, apply a first turn-on voltage to a selected string selection line among a plurality of string selection lines connected to a plurality of string selection transistors of the plurality of cell strings, apply a second turn-on voltage and a third turn on voltage to a first unselected string selection line and a second unselected string selection line respectively among the plurality of string selection lines in a selected memory block indicated by the address among the plurality of memory blocks,
wherein the decoder is further configured to, in response to the read command and in the selected memory block, apply a fourth turn-on voltage to a selected ground selection line among a plurality of ground selection lines connected to a plurality of ground selection transistors of the plurality of cell strings,
after applying the first through fourth turn-on voltages, in response to the read command and in the selected memory block, the decoder is further configured to adjust a first voltage of the first unselected string selection line to a first level,
after adjusting the first voltage of the first unselected string selection line, in response to the read command and in the selected memory block, the decoder is further configured to adjust a second voltage of the second unselected string selection line to a second level, and
string selection transistors, among the plurality of string selection transistors, connected to the selected string selection line and ground selection transistors, among the plurality of ground selection transistors, connected to the selected ground selection line are turned-on while the first voltage and the second voltage are adjusted in the selected memory block.
17. The storage device of claim 16 , wherein the first level is identical with the second level.
18. The storage device of claim 16 , wherein the first voltage having the first level turns-off string selection transistors, among the plurality of string selection transistors, connected to the first unselected string selection lines in the selected memory block.
19. The storage device of claim 16 , wherein the second voltage having the second level turns-off string selection transistors, among the plurality of string selection transistors, connected to the second unselected string selection lines in the selected memory block.
20. The storage device of claim 16 , wherein ground selection transistors, among the plurality of ground selection transistors, corresponding to the selected string selection line and the second unselected string selection line are connected to a same ground selection line among the plurality of ground selection lines in each of the plurality of memory blocks.