Semiconductor memory device and fabrication method thereof
A semiconductor memory device includes a memory gate disposed on a main surface of a substrate. The memory has a first sidewall and a second sidewall opposite to the first sidewall. A control gate is in proximity to the memory gate. The control gate has a third sidewall directly facing the second sidewall, and a fourth sidewall opposite to the third sidewall. A gap is provided between the second sidewall of the memory gate and the third sidewall of the control gate. A first single spacer structure is disposed on the first sidewall of the memory gate. A second single spacer structure is disposed on the fourth sidewall of the control gate. A gap-filling layer is deposited into the gap and fills up the gap.
1. A semiconductor memory device, comprising:
a substrate having a main surface;
a memory gate disposed on the main surface of the substrate, wherein the memory has a first sidewall and a second sidewall opposite to the first sidewall;
a control gate in proximity to the memory gate, wherein the control gate has a third sidewall directly facing the second sidewall, and a fourth sidewall opposite to the third sidewall;
a gap between the second sidewall of the memory gate and the third sidewall of the control gate;
a first single spacer structure on the first sidewall of the memory gate;
a second single spacer structure on the fourth sidewall of the control gate; and
a gap-filling layer filling up the gap, wherein the gap filling layer is in direct contact with the second sidewall and the third sidewall.
2. The semiconductor memory device according to claim 1 , wherein the first single spacer structure, the second single spacer structure and the gap filling layer all consist of only one layer of dielectric material.
3. The semiconductor memory device according to claim 2 , wherein said only one layer of dielectric material is a silicon nitride layer.
4. The semiconductor memory device according to claim 1 , wherein the first single spacer structure is in direct contact with the first sidewall and the main surface of the substrate, the second single spacer structure is in direct contact with the fourth sidewall and the main surface of the substrate.
5. The semiconductor memory device according to claim 1 , wherein the gap filling layer has a top surface that is flush with a top surface of the memory gate and a top surface of the control gate.
6. The semiconductor memory device according to claim 1 further comprising:
a first source/drain doping region disposed in the main surface of the substrate and adjacent to the first single spacer structure; and
a second source/drain doping region disposed in the main surface of the substrate and adjacent to the second single spacer structure.
7. The semiconductor memory device according to claim 1 further comprising:
a recessed region at a bottom of the gap.
8. The semiconductor memory device according to claim 1 , wherein the memory gate comprises an oxide-nitride-oxide (ONO) film, a polysilicon layer on the ONO film, and a cap layer on the polysilicon layer.
9. The semiconductor memory device according to claim 1 , wherein the control gate comprises a polysilicon layer.