Fan-out semiconductor package and electronic device including the same

1. A semiconductor package comprising:

a first interconnection member; and

a semiconductor chip disposed on the first interconnection member, and having an active surface on which connection pads are disposed and an inactive surface opposing the active surface in a thickness direction,

wherein the first interconnection member includes a first insulating layer, a first pad partially embedded in the first insulating layer, a second insulating layer disposed on the first insulating layer and being in physical contact with a surface of the first pad exposed from the first insulating layer, a first via penetrating through the first insulating layer, and a second via penetrating through the second insulating layer,

the first pad physically connects the first via and the second via, and is electrically connected to one of the connection pads of the semiconductor chip,

in an overlay view of the first via, the second via, and the first pad projected along the thickness direction, each of the first via and the second via is completely inside the first pad,

in the overlay view of the first via, the second via, and the first pad projected along the thickness direction, a center of the first via and a center of the second via are disposed on opposite sides of a center of the first pad, and

the first insulating layer is disposed below the second insulating layer with respect to an interface of the first interconnection member and the semiconductor chip.

2. The semiconductor package of claim 1 , wherein the first interconnection member further comprises:

a second pad partially embedded in the second insulating layer, and connected the first pad directly by the second via;

a third insulating layer disposed on the second insulating layer and being in physical contact with a surface of the second pad exposed from the second insulating layer;

a third via penetrating through the third insulating layer, and physically connected the second pad,

in an overlay view of the first to third vias, the first pad, and the second pad projected along the thickness direction, each of the first to third vias is completely inside each of the first pad and the second pad, and

in the overlay view of the first via, the second via, and the first pad projected along the thickness direction, a center of the third via and the center of the first via are disposed on a same side of the center of the first pad or on a same side of a center of the second pad, with respect to the center of the second via.

3. The semiconductor package of claim 1 , further comprising:

a passivation layer attached to the first insulating layer; and

a lowermost pad connected the first pad directly by the first via, and partially embedded in the passivation layer, a surface of the lowermost pad exposed from the passivation layer being in physical contact with the first insulating layer,

wherein the passivation layer has an opening exposing a portion of a lower surface of the lowermost pad.

4. The semiconductor package of claim 1 , further comprising:

a second interconnection member disposed on the first interconnection member and having a through-hole in which the semiconductor chip is disclosed; and

an encapsulant encapsulating portions of the second interconnection member and the semiconductor chip, and filling a portion of the through-hole.

5. The semiconductor package of claim 1 , wherein the first pad has a shape selected from a circular shape, an oval shape, and a rectangular shape.

6. The semiconductor package of claim 3 , wherein the first interconnection member includes a first region corresponding to a region in which the semiconductor chip is disposed, and a second region enclosing the first region, and

the opening of the passivation layer is disposed in a corner portion of the second region or a corner portion of the first region.

7. The semiconductor package of claim 3 , wherein the first interconnection member includes a first region corresponding to a region in which the semiconductor chip is disposed, and a second region enclosing the first region, and

the opening of the passivation layer is disposed in an outermost portion of the second region or an outermost portion of the first region.

8. The semiconductor package of claim 4 , further comprising redistribution layers disposed on opposite surfaces of the second interconnection member,

wherein the redistribution layers are electrically connected to the connection pads of the semiconductor chip.

9. The semiconductor package of claim 4 , wherein the second interconnection member includes an upper insulating layer and a lower insulating layer,

the semiconductor package further comprises:

a first redistribution layer disposed on an upper surface of the upper insulating layer;

a second redistribution layer disposed on a lower surface of the lower insulating layer; and

a third redistribution layer partially embedded in the lower insulating layer, a surface of the third redistribution layer exposed from the lower insulating layer being in physical contact with the upper insulating layer, and

the first to third redistribution layers are electrically connected to the connection pads of the semiconductor chip.

10. The semiconductor package of claim 4 , further comprising:

a first redistribution layer disposed on an upper surface of the second interconnection member; and

a second redistribution layer partially embedded in the second interconnection member, a surface of the second redistribution layer exposed from the second interconnection member being in physical contact with the first interconnection member,

wherein the first and second redistribution layers are electrically connected to the connection pads of the semiconductor chip.

11. The semiconductor package of claim 4 , wherein the second interconnection member includes an upper insulating layer and a lower insulating layer,

the semiconductor package further comprises:

a first redistribution layer disposed on an upper surface of the upper insulating layer;

a second redistribution layer partially embedded in the upper insulating layer, a surface of the second redistribution layer exposed from the upper insulating layer being in physical contact with the lower insulating layer; and

a third redistribution layer partially embedded in the lower insulating layer, a surface of the third redistribution layer exposed from the lower insulating layer being in physical contact with the first interconnection member; and

the first to third redistribution layers are electrically connected to the connection pads of the semiconductor chip.

12. A semiconductor package comprising:

a first interconnection member; and

a semiconductor chip disposed on the first interconnection member, and having an active surface on which connection pads are disposed and an inactive surface opposing the active surface in a thickness direction,

wherein the first interconnection member includes a first insulating layer, a first pad partially embedded in the first insulating layer, a first via penetrating through the first insulating layer and being in physical contact with the first pad, a second insulating layer disposed on the first insulating layer and being in physical contact with a surface of the first pad exposed from the first insulating layer, a second pad partially embedded in the second insulating layer, a second via penetrating through the second insulating layer and physically connecting the first pad and the second pad, a third insulating layer disposed on the second insulating layer and being in physical contact with a surface of the second pad exposed from the second insulating layer, and a third via penetrating through the third insulating layer and physically connected to the second pad,

the first pad and the second pad are electrically connected to one of the connection pads of the semiconductor chip,

in an overlay view of the first to third vias, the first pad, and the second pad projected along the thickness direction, each of the first to third vias is completely inside each of the first pad and the second pad,

in an overlay view of the first to third vias, the first pad, and the second pad projected along the thickness direction, two of centers of the first to third vias are located on opposite sides of a line connecting a center of the first pad and a remaining one of the centers of the first to third vias or on opposite sides of a line connecting a center of the second pad and the remaining one of the centers of the first to third vias, and

the first insulating layer is disposed below the second insulating layer with respect to an interface of the first interconnection member and the semiconductor chip, and the second insulating layer is disposed below the third insulating layer with respect to the interface of the first interconnection member and the semiconductor chip.

13. The semiconductor package of claim 12 , wherein the first interconnection member further includes a third pad partially embedded in the third insulating layer, a fourth insulating layer disposed on the third insulating layer and being in physical contact with a surface of the third pad exposed from the third insulating layer, and a fourth via penetrating through the fourth insulating layer and physically connected to the third pad,

in an overlay view of the first to fourth vias and the first to third pads projected along the thickness direction, each of the first to fourth vias is completely inside each of the first to third pads,

in the overlay view of the first to fourth vias and the first to third pads projected along the thickness direction, a line connecting centers of the first and third vias and a line a line connecting centers of the second and third vias cross each other, and

the third insulating layer is disposed below the fourth insulating layer with respect to the interface of the first interconnection member and the semiconductor chip.

14. The semiconductor package of claim 12 , further comprising:

a passivation layer attached to the first insulating layer; and

a lowermost pad connected the first pad directly by the first via, and partially embedded in the passivation layer, a surface of the lowermost pad exposed from the passivation layer being in direct contact with the first insulating layer,

wherein the passivation layer has an opening exposing a portion of a lower surface of the lowermost pad,

the first interconnection member includes a first region corresponding to a region in which the semiconductor chip is disposed, and a second region enclosing the first region, and

the opening of the passivation layer is disposed in a corner portion of the second region, a corner portion of the first region, an outermost portion of the second region, or an outermost portion of the first region.

15. The semiconductor package of claim 12 , further comprising:

a second interconnection member disposed on the first interconnection member and having a through-hole in which the semiconductor chip is disclosed; and

an encapsulant encapsulating portions of the second interconnection member and the semiconductor chip, and filling a portion of the through-hole.

16. The semiconductor package of claim 13 , wherein in the overlay view of the first to fourth vias and the first to third pads projected along the thickness direction, the line connecting centers of the first and third vias and the line a line connecting centers of the second and third vias cross each other at a center of one of the first to third pads.

17. The semiconductor package of claim 15 , further comprising redistribution layers disposed on opposite surfaces of the second interconnection member,

wherein the redistribution layers are electrically connected to the connection pads of the semiconductor chip.

18. The semiconductor package of claim 15 , wherein the second interconnection member includes an upper insulating layer and a lower insulating layer,

the semiconductor package further comprises:

a first redistribution layer disposed on an upper surface of the upper insulating layer;

a second redistribution layer disposed on a lower surface of the lower insulating layer; and

a third redistribution layer partially embedded in the lower insulating layer, a surface of the third redistribution layer exposed from the lower insulating layer being in physical contact with the upper insulating layer, and

the first to third redistribution layers are electrically connected to the connection pads of the semiconductor chip.

19. The semiconductor package of claim 15 , further comprising:

a first redistribution layer disposed on an upper surface of the second interconnection member; and

a second redistribution layer partially embedded in the second interconnection member, a surface of the second redistribution layer exposed from the second interconnection member being in physical contact with the first interconnection member,

wherein the first and second redistribution layers are electrically connected to the connection pads of the semiconductor chip.

20. The semiconductor package of claim 15 , wherein the second interconnection member includes an upper insulating layer and a lower insulating layer,

the semiconductor package further comprises:

a first redistribution layer disposed on an upper surface of the upper insulating layer;

a second redistribution layer partially embedded in the upper insulating layer, a surface of the second redistribution layer exposed from the upper insulating layer being in physical contact with the lower insulating layer; and

a third redistribution layer partially embedded in the lower insulating layer, a surface of the third redistribution layer exposed from the lower insulating layer being in physical contact with the first interconnection member; and

the first to third redistribution layers are electrically connected to the connection pads of the semiconductor chip.