IP Library › Granted Patent US 10,540,276
Granted Patent B2
US 10,540,276 · App. 16/039,787 · Granted Jan 21, 2020

Method of processing data based on erase operations of logical pages related to data compression rate of mapping table in data storage device

Inventor: Wen-Sheng Lin (Kaohsiung, TW)
Assignee: Silicon Motion, Inc.
G06F12/0246G06F3/061G06F3/064G06F3/0652G06F3/0679G06F12/1009G06F13/24G11C11/5635G11C16/16G06F2212/401G06F2212/652G06F2212/7201G06F2212/7203G11C2211/5641
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Quick Facts
Patent No.
US 10,540,276
App. No.
16/039,787
Granted
Jan 21, 2020
Kind
B2
Abstract

A data storage device includes a memory device, an SRAM and a controller. The memory device includes a first buffer configured to store data of a plurality of consecutive logical pages. The SRAM stores a first mapping table. The first mapping table records which logical page the data stored in each physical page of the first buffer directs to. The controller is coupled to the memory device and the SRAM. When the controller performs an erase operation to erase the data stored in the first buffer in response to an erase command, the controller checks whether an interrupt signal or a reset command issued by a host device has been received every time the erase operations of a predetermined number (M) of logical pages have finished. The predetermined number (M) is a positive integer greater than 1.

Claims (17)

1. A data storage device, comprising:

a memory device, comprising a first buffer configured to store data of a plurality of consecutive logical pages;

a Static Random Access Memory (SRAM), configured to store a first mapping table, wherein the first mapping table records which logical page the data stored in each physical page of the first buffer directs to; and

a controller, coupled to the memory device and the SRAM, wherein when the controller performs an erase operation to erase the data stored in the first buffer in response to an erase command, the controller checks whether an interrupt signal or a reset command issued by a host device has been received every time the erase operations of a predetermined number (M) of logical pages have finished, wherein the predetermined number (M) is a positive integer greater than 1.

2. The data storage device as claimed in claim 1 , wherein the predetermined number is related to a data compression rate (R) of the first mapping table, and wherein the data compression rate (R) is a positive integer greater than 1.

3. The data storage device as claimed in claim 2 , wherein the controller is configured to edit the first mapping table according to the data compression rate (R), and wherein information regarding a portion of the logical pages having data stored in the first buffer is not recorded in the first mapping table.

4. The data storage device as claimed in claim 1 , wherein for every R consecutive logical pages having data stored in the first buffer, information regarding only one logical page is stored in the first mapping table, and wherein R is a positive integer greater than 1.

5. The data storage device as claimed in claim 1 , wherein the predetermined number (M) is an integer multiple of a data compression rate (R) of the first mapping table.

6. The data storage device as claimed in claim 1 , wherein the first buffer is configured to store data of a specific number (N) of consecutive logical pages, and wherein the specific number (N) is related to a size of one logical page and a size of one physical page.

7. A method for processing data stored in a memory device, suitable for a data storage device comprising a memory device, a Static Random Access Memory (SRAM) and a controller, the memory device comprising a first buffer configured to store data of a plurality of consecutive logical pages, the SRAM being configured to store a first mapping table, the method comprising:

editing, by the controller, the first mapping table according to a data compression rate (R), wherein the first mapping table records which logical page the data stored in each physical page of the first buffer directs to, and wherein information regarding a portion of the logical pages having data stored in the first buffer is not recorded in the first mapping table;

performing, by the controller, an erase operation to erase the data stored in the first buffer in response to an erase command; and

when performing the erase operation to erase the data stored in the first buffer in response to the erase command,

checking, by the controller, whether an interrupt signal or a reset command issued by a host device has been received every time the erase operations of a predetermined number (M) of logical pages have finished, wherein the predetermined number (M) is a positive integer greater than 1, and wherein the predetermined number is related to the data compression rate (R) of the first mapping table.

8. The method as claimed in claim 7 , wherein the predetermined number (M) is an integer multiple of the data compression rate (R) of the first mapping table.

9. The method as claimed in claim 7 , wherein for every R consecutive logical pages having data stored in the first buffer, information regarding only one logical page is stored in the first mapping table.

10. The method as claimed in claim 7 , wherein the first buffer is configured to store data of a specific number (N) of consecutive logical pages, and wherein the specific number (N) is related to a size of one logical page and a size of one physical page.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 19, 2018
From: LIN, WEN-SHENG
To: SILICON MOTION, INC.
Reel/Frame 046401/0118 →
Priority Claims (1)
TW 106144391 A · Dec 18, 2017 · national
Continuity (1)
Related Publication 20190188125A1 · Jun 20, 2019