III-nitride material semiconductor structures on conductive silicon substrates
III-nitride materials are described herein, including material structures comprising III-nitride material regions (e.g., gallium nitride material regions). In certain cases, the material structures also comprise substrates having relatively high electrical conductivities. Certain embodiments include one or more features that reduce the degree to which thermal runaway occurs, which can enhance device performance including at elevated flange temperatures. Some embodiments include one or more features that reduce the degree of capacitive coupling exhibited during operation. For example, in some embodiments, relatively thick III-nitride material regions and/or relatively small ohmic contacts are employed.
1. A semiconductor device, comprising:
a substrate, at least a portion of which is made of silicon having an electronic resistivity of less than 0.10 Ω-cm when the silicon is at 25° C.;
a III-nitride material region located over the substrate;
an ohmic contact over the III-nitride material region, the ohmic contact defining an ohmic contact interfacial area with the III-nitride material region; and
a gate electrode over the III-nitride material region, the gate electrode defining a gate electrode interfacial area with the III-nitride material region, wherein
the ohmic contact interfacial area is less than 50 times the gate electrode interfacial area.
2. The semiconductor device of claim 1 , wherein the semiconductor device is configured to operate at a frequency greater than 50 MHz.
3. The semiconductor device of claim 1 , wherein the semiconductor device is an active device.
4. The semiconductor device of claim 1 , wherein the semiconductor device is a discrete component.
5. The semiconductor device of claim 1 , wherein the substrate includes a silicon-on-insulator structure.
6. The semiconductor device of claim 1 , wherein the III-nitride material region comprises a gallium nitride material.
7. The semiconductor device of claim 1 , wherein the III-nitride material region comprises:
a nucleation layer formed over the substrate;
a buffer layer formed over the nucleation layer; and
a device region formed over the buffer layer.
8. The semiconductor device of claim 7 , further comprising a transition layer located between the nucleation layer and the buffer layer.
9. The semiconductor device of claim 8 , wherein the transition layer is a superlattice.
10. The semiconductor device of claim 8 , wherein the transition layer is compositionally graded.
11. The semiconductor device of claim 7 , wherein the semiconductor device is formed, at least in part, in the device region.
12. The semiconductor device of claim 11 , wherein the semiconductor device is a transistor or a diode.
13. The semiconductor device of claim 12 , wherein the transistor or diode is configured to operate at a frequency between 100 MHz and 20 GHz.
14. The semiconductor device of claim 12 , wherein the transistor or diode has an active-area capacitance ratio that is no larger than 0.4 pF/mm.
15. The semiconductor device of claim 12 , wherein an amount of power dissipated into the substrate due to capacitive coupling between components of the transistor or diode and the substrate is no larger than 0.1 Watts/mm 2 when a temperature of the substrate is at 120° C.
16. The semiconductor device of claim 12 , wherein a power added efficiency of the transistor remains above 50% when a temperature of the substrate is increased to 125° C.
17. A semiconductor device, comprising:
a substrate, at least a portion of which comprises silicon having an electronic resistivity of less than 0.10 Ω-cm when the silicon is at 25° C.;
a III-nitride material region located over the substrate;
an ohmic contact over the III-nitride material region, the ohmic contact defining an ohmic contact interfacial area with the III-nitride material region; and
a gate electrode over the III-nitride material region, the gate electrode defining a gate electrode interfacial area with the III-nitride material region, wherein:
the ohmic contact interfacial area is less than 50 times the gate electrode interfacial area; and
the semiconductor device is configured to operate at a frequency greater than 50 MHz, wherein the substrate comprises bulk silicon or silicon carbide.