Quasi-resonant valley lockout without feedback reference
View Patent ↗A method of controlling a power supply includes detecting a transition of the power supply to discontinuous conduction mode (DCM), and locking an operating point of the power supply after detecting the transition. The operating point can be unlocked when a timer expires or when a feedback voltage slope exceeds a threshold.
1. A power supply controller, comprising:
a zero current detection (ZCD) terminal;
a first counter comprising a clock terminal of the first counter coupled to the ZCD terminal;
a second counter comprising a clock terminal of the second counter coupled to the ZCD terminal; and
a control circuit configured to enable the first counter to acquire a threshold, enable the second counter when the first counter has a threshold stored, and assert a control output of the power supply controller when a value of the second counter is equal to a value of the first counter.
2. The power supply controller of claim 1 , further including a slow clock, wherein the control circuit is configured to reset and enable the first counter based on the slow clock.
3. The power supply controller of claim 1 , wherein the control circuit is configured to stop the first counter when the control output is asserted.
4. The power supply controller of claim 1 , wherein the control circuit is configured to reset the second counter based on a comparison between a current sense input of the power supply controller and a feedback input of the power supply controller.
5. The power supply controller of claim 4 , further including a low pass filter for the feedback input.
6. The power supply controller of claim 1 , further including a valley lockout escape signal generation circuit configured to reset and enable the first counter when a rate of change of a feedback input signal of the power supply controller exceeds a threshold.
7. The power supply controller of claim 1 , further including a comparator comprising a first input of the comparator coupled to the ZCD terminal, a second input of the comparator coupled to a reference voltage potential, and an output of the comparator coupled to the clock terminal of the first counter and the clock terminal of the second counter.
8. A power supply controller, comprising:
a zero current detection (ZCD) terminal;
a first counter configured to count a first plurality of pulses received on the ZCD terminal;
a second counter configured to count a second plurality of pulses received on the ZCD terminal; and
a control circuit configured to assert a control output of the power supply controller when a value of the first counter is equal to a value of the second counter.
9. The power supply controller of claim 8 , wherein the ZCD terminal is coupled to a clock input of the first counter and a clock input of the second counter.
10. The power supply controller of claim 8 , further including a slow clock configured to reset and enable the first counter.
11. The power supply controller of claim 8 , wherein the first counter is configured to stop counting when the control output is asserted.
12. The power supply controller of claim 8 , further including a pulse-width modulation (PWM) block configured to compare a current sense input of the power supply controller against a feedback input of the power supply controller and reset the second counter.
13. The power supply controller of claim 12 , wherein the PWM block includes a low pass filter.
14. The power supply controller of claim 8 , further including a valley lockout escape signal generation circuit configured to reset and enable the first counter when a rate of change of a feedback input signal of the power supply controller exceeds a threshold.
15. A power supply controller, comprising:
a first counter configured to acquire a reference valley number;
a second counter configured to determine an instantaneous valley number;
a zero current detection terminal coupled to a clock input of the first counter and a clock input of the second counter; and
a comparator coupled to an output of the first counter and an output of the second counter.
16. The power supply controller of claim 15 , further including:
a feedback circuit node;
a low-pass filter (LPF) coupled to the feedback circuit node;
a voltage-controlled oscillator (VCO) coupled to the feedback circuit node through the LPF; and
an OR gate including a first input coupled to the VCO and a second input coupled to the comparator.
17. The power supply controller of claim 15 , further including a slope detection circuit coupled to a feedback input of the power supply controller and configured to reset the first counter.
18. The power supply controller of claim 15 , further including a timer configured to reset the first counter.
19. The power supply controller of claim 15 , further including a pulse generator coupled to an output of the comparator.