Trench diode and method of forming the same

1. A method for forming a trench diode for a power semiconductor device, the method comprising:

forming a first trench having a first opening and a second trench having a second opening in a substrate material, the second opening of the second trench being wider than the first opening of the first trench;

forming an insulating layer over surfaces of the first and second trenches;

providing a first semiconductor material within the first and second trenches, the first semiconductor material filling the first trench at least until the first opening is entirely plugged with the first semiconductor material, the first semiconductor material partially filling the second trench so that a portion of the second opening remains open, the first semiconductor material having a first conductivity type; and

providing a second semiconductor material within the second trench and over the first semiconductor material, the second semiconductor material having a second conductivity type that is different from the first conductivity type,

wherein the first semiconductor material and the second semiconductor material provided within the second trench define a P-N junction of the trench diode.

2. The method of claim 1 , further comprising:

providing a semiconductor substrate; and

growing an epi layer over the semiconductor substrate,

wherein the substrate material includes the semiconductor substrate and the epi layer, the first and second trenches being formed in the epi layer.

3. The method of claim 1 , wherein the first semiconductor material is deposited to have a given thickness, so that the first opening of the first trench is entirely plugged with the first semiconductor material and a portion of the second opening of the second trench remains open, and

wherein the trench diode is a Zener diode for electrostatic discharge (ESD) protection of the power semiconductor device.

4. The method of claim 3 , wherein the first opening of the first trench has a first width and the second opening of the second trench has a second width, the given thickness of the first semiconductor material being about 30% to about 50% of the second width of the second trench.

5. The method of claim 3 , wherein the second opening of the second trench is at least 2.5 times wider than the first opening of the first trench.

6. The method of claim 1 , wherein the first trench defines a gate trench for the power semiconductor device and the first semiconductor material provided within the first trench defines a gate structure for the power semiconductor device.

7. The method of claim 1 , wherein the first semiconductor material and the second semiconductor material include a polysilicon material, and the first conductivity type is an N type conductivity and the second conductivity type is a P type conductivity.

8. The method of claim 1 , wherein the insulating layer has a sufficient thickness to avoid a breakdown between the trench diode and the substrate material.

9. The method of claim 1 , wherein the trench diode is a Zener diode for electrostatic discharge (ESD) protection of the power semiconductor device and a breakdown voltage of the trench diode is adjusted by controlling a doping concentration of the second semiconductor material.

10. The method of claim 1 , further comprising:

implanting impurities of the second conductivity type into the second semiconductor material to form a third semiconductor layer within the second trench, the third semiconductor layer having a higher doping concentration than that of the second semiconductor material.

11. The method of claim 10 , further comprising implanting impurities of the second conductivity type into the substrate material to form a body region for the power semiconductor device,

wherein the implanting step for the third semiconductor layer and the implanting step for the body region occur simultaneously.