High speed radar test system processing and logic
A radar test computing system includes a host interface coupled to a programmable input/output (I/O) controller, which is to interface with propagation path replicator (PPR) circuitry. A processing device is to detect a start signal received from the controller; receive an update request from the controller in response to detection, by the PPR circuitry, of a first radio RF pulse on a RF signal received from the radar system; retrieve scenario data of distance to and speed of the moving target for a second RF pulse expected to follow the first RF pulse; calculate, using retrieved scenario data, values of a frequency shift, a signal delay, and a signal attenuation for the second RF pulse; and send, during a time period between the first and second RF pulses, these values to the controller for use by the PPR circuitry to simulate the moving target for the second RF pulse.
1. A radar test computing system comprising:
a storage disk to store scenario data for a test scenario;
a host interface to be coupled to a programmable input/output (I/O) controller, wherein the programmable I/O controller is to interface with propagation path replicator (PPR) circuitry that is to simulate a moving target for a radar system under test; and
a processing device coupled to the storage disk and the host interface, wherein the processing device is to:
detect a start signal received from the programmable I/O controller, the start signal received by the programmable I/O controller from the radar system to trigger initiation of the test scenario;
receive an update request from the programmable I/O controller in response to detection, by the PPR circuitry, of a first radio frequency (RF) pulse on a RF signal received from the radar system;
retrieve the scenario data associated with distance to and speed of the moving target for a second RF pulse expected to follow the first RF pulse;
calculate, using retrieved scenario data, values of a frequency shift, a signal delay, and a signal attenuation for the second RF pulse; and
send, during a time period between the first RF pulse and the second RF pulse, the values of the frequency shift, the signal delay, and the signal attenuation to the programmable I/O controller for use by the PPR circuitry to simulate the moving target for the second RF pulse.
2. The radar test computing system of claim 1 , wherein to calculate a value of:
the frequency shift, the processing device is to determine, based on the retrieved scenario data, the speed of the moving target at a time of the second RF pulse;
the signal delay, the processing device is to determine, based on the retrieved scenario data, the distance to the moving target at the time of the second RF pulse; and
the signal attenuation, the processing device is to determine, based on the retrieved scenario data, a position of and the distance to the moving target at the time of the second RF pulse.
3. The radar test computing system of claim 1 , further comprising a user interface coupled to the processing device and viewable through a display device, wherein the processing device is further to:
detect, through the user interface, opening of the test scenario;
in response to detection of the opening of the test scenario, send a portion of the scenario data to the programmable I/O controller; and
send a disarm message to the programmable I/O controller.
4. The radar test computing system of claim 3 , wherein the processing device is further to:
detect, through the user interface, a command to arm the test scenario; and
arm the test scenario comprising to send an arm message to the programmable I/O controller, wherein once armed, the programmable I/O controller is to monitor for the start signal through an RF start trigger line coupled to the radar system.
5. The radar test computing system of claim 1 , wherein to receive the update request further comprises to receive status data from the programmable I/O controller, the status data comprising values for timing data associated with the first RF pulse, further comprising a user interface coupled to the processing device and viewable through a display device, and wherein the processing device is further to:
update a scenario table, within the user interface, with the status data; and
update a scenario plot, within the user interface, with the values of the frequency shift, the signal delay, and the signal attenuation for the second RF pulse.
6. The radar test computing system of claim 5 , wherein the storage disk is further to store second scenario data for a second test scenario, wherein the processing device is further to:
detect an end of the test scenario;
write the status data to a log file in the storage disk;
auto-load the second scenario data; and
send a portion of the second scenario data to the programmable I/O controller in preparation to perform the second test scenario.
7. The radar test computing system of claim 5 , wherein the processing device is further to:
detect, through the user interface, selection of a stop indicia to stop the test scenario;
write the status data to a log file in the storage disk; and
send a disarm message to the programmable I/O controller.
8. The radar test computing system of claim 5 , wherein the status data indicates the second RF pulse did not arrive within a timeout period, and the processing device is further to update the scenario table and the scenario plot with a missing pulse for the second RF pulse.
9. A programmable input/output (I/O) controller coupled to a radar test computing system and comprising a programmable logic device to:
reset status data values related to timing of radio frequency (RF) pulses received on a RF signal from a radar system under test with respect to a moving target, wherein the status data values comprise at least values for a running time, an elapsed time, and pre-pulse counts;
in response to detection of an arm message from the radar test computing system, monitor for one of a start message or a stop message;
in response to receipt of the start message from the radar test computing system, set the running time to a current time and the elapsed time to zero; and
in response to reaching a timeout period before detecting a first qualified pulse on the RF signal from the radar system:
update a value for the elapsed time;
increment a value for the pre-pulse counts;
send values for the elapsed time and pre-pulse counts to the radar test computing system; and
send an update request to the radar test computing system to request values of a frequency shift, a signal delay, and a signal attenuation for the first qualified pulse anticipated within a subsequent timeout period, wherein the frequency shift is to simulate speed of the moving target, the signal delay to simulate a distance from the moving target, and the signal attenuation is to simulate an amount of atmospheric propagation loss.
10. The programmable I/O controller of claim 9 , wherein the programmable logic device is further to:
receive a reference voltage in scenario data from the radar test computing system before receipt of the start message; and
provide the reference voltage to a comparator of a pulse detection circuit, which detects the qualified pulse on behalf of the programmable logic device.
11. The programmable I/O controller of claim 9 , wherein the programmable logic device is further to, before receipt of the first qualified pulse:
receive values from the radar test computing system for the frequency shift, the signal delay, and the signal attenuation;
update a Doppler simulation circuit, coupled to the programmable logic device, with the frequency shift;
update a signal attenuator, coupled to the programmable logic device, with the signal attenuation; and
update a signal delay sub-system, coupled to the programmable logic device, with the signal delay.
12. The programmable I/O controller of claim 9 , wherein the status data values further comprise values for a post pulse time, pulse counts, pulse width total counts, and a pulse repeating interval (PRI) total counts, and wherein the programmable logic device is further to, in response to detection of the first qualified pulse on the RF signal from the radar system:
update the value for the elapsed time;
set a value for the post pulse time to the current time;
increment a value for the pulse counts;
update a value for the pulse width total counts;
update a value for the PRI total counts;
send the status data values to the radar test computing system; and
send an update request to the radar test computing system to request values of a second frequency shift, a second signal delay, and a second signal attenuation for a second qualified pulse anticipated within a second subsequent timeout period.
13. The programmable I/O controller of claim 12 , wherein the programmable logic device is further to, before receipt of the second qualified pulse:
receive values from the radar test computing system for the second frequency shift, the second signal delay, and the second signal attenuation;
update a Doppler simulation circuit, coupled to the programmable logic device, with the second frequency shift;
update a signal attenuator, coupled to the programmable logic device, with the second signal attenuation; and
update a signal delay sub-system, coupled to the programmable logic device, with the second signal delay.
14. The programmable I/O controller of claim 12 , wherein the status data values further comprise a value for missing pulse counts, and wherein the programmable logic device is further to, in response to reaching a timeout period before receipt of the second qualified pulse:
update the value for the elapsed time;
increment the value for the missing pulse counts;
send the values for the elapsed time and the missing pulse counts to the radar test computing system; and
send an update request to the radar test computing system to request values of a third frequency shift, a third signal delay, and a third signal attenuation for an third qualified pulse anticipated within a third subsequent timeout period.
15. The programmable I/O controller of claim 14 , wherein in response to receipt of the third qualified pulse, the programmable logic device is further to synchronize a time for a fourth subsequent timeout period to a trailing edge of the third qualified pulse.
16. The programmable I/O controller of claim 12 , wherein the programmable logic device is further to, in response to detection of the second qualified pulse:
update the value for the elapsed time;
increment the value for the pulse counts;
update the value for the pulse width total counts;
update the value for the PRI total counts;
send the status data values to the radar test computing system; and
send an update request to the radar test computing system to request values of a third frequency shift, a third signal delay, and a third signal attenuation for a third qualified pulse anticipated within a third subsequent timeout period.
17. A method comprising:
coupling a host interface, of a radar test computing system, to a programmable input/output (I/O) controller, wherein the programmable I/O controller is to interface with propagation path replicator (PPR) circuitry that is to simulate a moving target for a radar system under test;
receiving, by the radar test computing system from a signal analyzer circuit, a start message indicative of a start pulse detected by the signal analyzer circuit, which is coupled to the radar test computing system and to the PPR circuitry, wherein the start pulse is to trigger initiation of a test scenario;
receiving, by the radar test computing system, an update request from the programmable I/O controller in response to detection, by the PPR circuitry, of a first radio frequency (RF) pulse on a RF signal received from the radar system;
retrieving, by the radar test computing system from a storage disk, scenario data associated with distance to and speed of the moving target for a second RF pulse expected to follow the first RF pulse;
calculating, by a processing device of the radar test computing system, using retrieved scenario data, values of a frequency shift, a signal delay, and a signal attenuation for the second RF pulse; and
sending, by the radar test computing system, during a time period between the first RF pulse and the second RF pulse, the values of the frequency shift, the signal delay, and the signal attenuation to the programmable I/O controller for use by the PPR circuitry to simulate the moving target for the second RF pulse.
18. The method of claim 17 , wherein the calculating:
the frequency shift based on the scenario data comprises determining the speed of the moving target at a time of the second RF pulse;
the signal delay based on the scenario data comprises determining the distance to the moving target at a time of the second RF pulse; and
the signal attenuation based on the scenario data comprises determining a position of and the distance to the moving target at a time of the second RF pulse.
19. The method of claim 17 , further comprising:
detecting, through a user interface of the radar test computing system, opening of the test scenario;
in response to detection of the opening of the test scenario, sending a portion of the scenario data to the programmable I/O controller and to the signal analyzer circuit; and
sending a disarm message to the programmable I/O controller and the signal analyzer circuit.
20. The method of claim 19 , further comprising:
detecting, through the user interface, a command to arm the test scenario; and
arming the test scenario comprising sending an arm message to the programmable I/O controller and to the signal analyzer circuit, wherein once armed, the signal analyzer circuit is to monitor for the start pulse received from the PPR circuitry.
21. The method of claim 17 , further comprising:
detecting, through a user interface, a selection to execute an analyzer application associated with the signal analyzer circuit;
receive, through the user interface, selection of a set of analyzer modes; and
executing, by the processing device, the analyzer application to cause the signal analyzer circuit to perform functions, based on the set of analyzer modes and associated with a swept tuned spectrum analyzer, on the RF signal received from the PPR circuitry.
22. The method of claim 17 , wherein receiving the update request further comprises receiving status data from the programmable I/O controller, the status data comprising values for timing data associated with the first RF pulse, further comprising:
updating a scenario table with the status data;
updating a scenario plot with the values of the frequency shift, the signal delay, and the signal attenuation for the second RF pulse; and
displaying the scenario table and the scenario plot within a user interface of a display device of the radar test computing system.
23. The method of claim 22 , further comprising:
detecting an end of the test scenario;
writing the status data to a log file in the storage disk;
auto-loading second scenario data from the storage disk for a second test scenario; and
sending a portion of the second scenario data to the programmable I/O controller and the signal analyzer circuit in preparation to perform the second test scenario.
24. The method of claim 22 , further comprising:
detecting, through the user interface, selection of a stop indicia to stop the test scenario;
writing the status data to a log file in the storage disk; and
sending a disarm message to the programmable I/O controller and the signal analyzer circuit.
25. The method of claim 22 , wherein the status data indicates the second RF pulse did not arrive within a timeout period, the method further comprising updating the scenario table and the scenario plot with a missing pulse for the second RF pulse.