Method for forming channel hole plug of three-dimensional memory device
Embodiments of a channel hole plug structure of 3D memory devices and fabricating methods thereof are disclosed. The memory device includes an alternating layer stack disposed on a substrate, an insulating layer disposed on the alternating dielectric stack, a channel hole extending vertically through the alternating dielectric stack and the insulating layer, a channel structure including a channel layer in the channel hole, and a channel hole plug in the insulating layer and above the channel structure. The channel hole plug is electrically connected with the channel layer. A projection of the channel hole plug in a lateral plane covers a projection of the channel hole in the lateral plane.
1. A method for forming a channel hole plug structure in a three-dimensional (3D) memory device, comprising:
forming an alternating dielectric stack disposed on a substrate;
forming a first insulating layer on the alternating dielectric stack;
forming a channel structure penetrating the first insulating layer and the alternating dielectric stack, wherein the channel structure includes a functional layer, a channel layer, and a filling structure;
forming a second insulating layer directly on the first insulating layer and the channel structure;
forming a hard mask layer directly on the second insulating layer;
forming a photoresist layer directly on the hard mask layer;
forming an opening in the hard mask layer and the photoresist layer to expose the second insulating layer, wherein a diameter of the opening in a lateral plane is larger than a diameter of a top surface of the channel structure;
removing, using the hard mask layer or the photoresist layer as a mask, a portion of the second insulating layer above the channel structure to form a recess in the first and second insulating layers, wherein a bottom aperture of the recess exposes the top surface of the channel structure;
forming a semiconductor layer in the recess and on the hard mask layer, wherein the semiconductor layer is formed using a same semiconductor material of the channel layer, and in contact with the channel layer; and
removing the hard mask layer and a top portion of the semiconductor layer, such that a remaining portion of the semiconductor layer embedded in the first and second insulating layers forms a channel hole plug in the recess, wherein a diameter of the channel hole plug in a lateral plane is larger than the diameter of the top surface of the channel structure.
2. The method of claim 1 , wherein forming the alternating dielectric stack comprises:
forming at least 32 dielectric layer pairs stacked in a vertical direction, each dielectric layer pair includes a first dielectric layer and a second dielectric layer that is different from the first dielectric layer.
3. The method of claim 1 , wherein forming the channel structure comprises:
forming a channel hole extending vertically through the alternating dielectric stack and the first insulating layer;
forming the functional layer on a sidewall of the channel hole;
forming the channel layer covering a sidewall of the functional layer; and
forming the filling structure to cover a sidewall of the channel layer and filling the channel hole.
4. The method of claim 3 , wherein forming the functional layer comprises:
forming a barrier layer on the sidewall of the channel hole for blocking an outflow of the electronic charges;
forming a storage layer on a surface of the barrier layer for storing electronic charges during operation of the 3D memory device; and
forming a tunneling layer on a surface of the storage layer for tunneling electronic charges.
5. The method of claim 1 , wherein forming the second insulating layer, the hard mask layer and the photoresist patterning comprises:
forming an oxide layer on the first insulating layer and the channel structure as the second insulating layer;
forming a nitride layer on the oxide layer as the hard mask layer; and
forming a photoresist layer on the nitride layer.
6. The method of claim 2 , further comprising:
performing a gate replacement process to replace first dielectric layers with conductor layers.
7. The method of claim 1 , wherein:
the first insulating layer and the second insulating layer have a same material and form a plug insulating layer.
8. The method of claim 1 , further comprising:
forming a metal via above the channel hole plug for electronically connecting the channel hole plug.
9. The method of claim 1 , further comprising:
forming a second alternating dielectric stack on the second insulating layer and the channel hole plug; and
forming a second channel structure penetrating the second alternating dielectric stack, wherein a second channel layer in the second channel structure is electrically in contact with the channel hole plug.