Three-dimensional memory device and fabricating method thereof
Embodiments of through array contact structures of a 3D memory device and fabricating method thereof are disclosed. The method comprises: forming a recess region in a substrate including multiple protruding islands; forming a gate dielectric layer to cover top surfaces and sidewalls of the multiple protruding islands and a top surface of the recess region of the substrate; forming an underlying sacrificial layer on the gate dielectric layer to surround the sidewalls of the multiple protruding islands; forming an alternating dielectric stack including multiple alternatively stacked insulating layers and sacrificial layers on the underlying sacrificial layer and the multiple protruding islands; forming multiple channel holes penetrating the alternating dielectric stack, each channel hole is located corresponding to one of the multiple protruding islands; and forming a memory layer in each channel hole, wherein a channel layer of the memory layer is electrically connected with a corresponding protruding island.
1. A three-dimensional (3D) NAND memory device, comprising:
a substrate including a plurality of monolithic protruding islands in a recess region of the substrate;
a gate dielectric layer completely covering sidewalls of the plurality of protruding islands and a top surface of the recess region of the substrate, wherein the gate dielectric layer is a continuous piece;
an underlying conductor layer contacting the gate dielectric layer in both a lateral direction and a vertical direction, and surrounding the sidewalls of the plurality of protruding islands in a lateral plane;
an alternating conductor/dielectric stack including a plurality of alternatively stacked insulating layers and conductor layers on the underlying conductor layer and the plurality of protruding islands;
a plurality of channel holes vertically penetrating the alternating conductor/dielectric stack, each channel hole is above one protruding island; and
a memory layer in each channel hole, wherein a channel layer of the memory layer is electrically connected with a corresponding protruding island.
2. The device of claim 1 , wherein the plurality of protruding islands is formed by etching the substrate.
3. The device of claim 1 , wherein the plurality of protruding islands is arranged in an array.
4. The device of claim 1 , wherein a height of the underlying conductor layer is lower than a height of each protruding island.
5. The device of claim 1 , wherein a top surface of the underlying conductor layer is lower than a top surface of each protruding island.
6. The device of claim 1 , wherein a top surface of each protruding island is lower than a top surface of a lowest insulating layer in the alternating conductor/dielectric stack.
7. The device of claim 1 , wherein the insulating layers comprise silicon oxide.
8. The device of claim 1 , wherein the underlying conductor layer and the conductor layers comprise tungsten.
9. The device of claim 1 , wherein the memory layer in each channel hole comprises:
a charge trapping layer on a sidewall of each channel hole;
a channel layer in contact with a protruding island on a sidewall of the charge trapping layer; and
an insulation filling layer filling a gap in the channel layer.
10. The device of claim 1 , further comprising:
a drain contact at a top portion of each channel hole;
wherein each of the plurality of protruding islands acts as a channel region of a source line selector at a bottom portion of each channel hole.