Semiconductor memory device with a three-dimensional stacked memory cell structure
A semiconductor memory device comprises: a semiconductor substrate; a plurality of memory units provided on the semiconductor substrate and each including a plurality of memory cells that are stacked; and a plurality of bit lines formed above each of a plurality of the memory units aligned in a column direction, an alignment pitch in a row direction of the plurality of bit lines being less than an alignment pitch in the row direction of the memory units, and an end of each of the memory units aligned in the column direction being connected to one of the plurality of bit lines formed above the plurality of the memory units aligned in the column direction.
1. A semiconductor memory device, comprising:
a semiconductor substrate;
a memory unit array including a first area in which a first memory unit is located and a second area in which a second memory unit is located;
a first bit line disposed above the first memory unit and the second memory unit;
a first bit line contact connected to the first memory unit and the first bit line;
a second bit line disposed above the first memory unit and the second memory unit, and along with the first bit line; and
a second bit line contact connected to the second memory unit and the second bit line,
wherein in the first area the first bit line contact is displaced to one side of a center line connecting a center position of the first memory unit and a center position of the second memory unit, and in the second area the second bit line contact is displaced to the other side of the center line.
2. The semiconductor memory device according to claim 1 , wherein
the first memory unit includes a first memory cell and a second memory cell stacked in a first direction, the first direction crossing the substrate, and
the second memory unit includes a third memory cell and a fourth memory cell stacked in the first direction.
3. The semiconductor memory device according to claim 1 , further comprising:
a third memory unit located in a third area and a fourth memory unit located in a fourth area;
a third bit line disposed above the third memory unit and the fourth memory unit, and along with the second bit line;
a third bit line contact connected to the third memory unit and the third bit line;
a fourth bit line disposed above the third memory unit and the fourth memory unit, and along with the third bit line; and
a fourth bit line contact connected to the fourth memory unit and the fourth bit line,
wherein in the third area the third bit line contact is displaced to the one side of the center line, and in the fourth area the fourth bit line contact is displaced to the other side of the center line.
4. The semiconductor memory device according to claim 3 , further comprising:
a first line connected to the first memory unit and the third memory unit; and
a second line connected to the second memory unit and the fourth memory unit.
5. The semiconductor memory device according to claim 4 , further comprising:
a third line connected to the first memory unit and the third memory unit, the third line and the first line being stacked in a first direction, the first direction crossing the substrate; and
a fourth line connected to the second memory unit and the fourth memory unit, the fourth line and the second line being stacked in the first direction.
6. The semiconductor memory device according to claim 2 , wherein
a read or write operation is performed to the first memory cell and the third memory cell simultaneously.
7. The semiconductor memory device according to claim 1 , further comprising:
a sense amplifier connected selectively or simultaneously to the first bit line and the second bit line.
8. The semiconductor memory device according to claim 7 , wherein a differential type sense amplifier is used as the sense amplifier.
9. A semiconductor memory device, comprising:
a semiconductor substrate;
a memory unit array including a first area in which a first memory unit is located and a second area in which a second memory unit is located;
a bit line disposed above the first memory unit and the second memory unit;
a first bit line contact connected to the first memory unit and the bit line;
a second bit line contact connected to the second memory unit and the bit line,
wherein in the first area the first bit line contact is displaced to one side of a center line connecting a center position of the first memory unit and a center position of the second memory unit, and in the second area the second bit line contact is displaced to the other side of the center line.
10. The semiconductor memory device according to claim 9 , wherein
the first memory unit includes a first memory cell and a second memory cell stacked in a first direction, the first direction crossing the substrate, and
the second memory unit includes a third memory cell and a fourth memory cell stacked in the first direction.
11. The semiconductor memory device according to claim 9 , further comprising:
a third memory unit located in a third area and a fourth memory unit located in a fourth area;
a second bit line disposed above the third memory unit and the fourth memory unit, and along with the bit line;
a third bit line contact connected to the third memory unit and the second bit line;
a third bit line disposed above the third memory unit and the fourth memory unit, and along with the second bit line; and
a fourth bit line contact connected to the fourth memory unit and the third bit line,
wherein in the third area the third bit line contact is displaced to the one side of the center line, and in the fourth area the fourth bit line contact is displaced to the other side of the center line.
12. The semiconductor memory device according to claim 11 , further comprising:
a first line connected to the first memory unit and the third memory unit; and
a second line connected to the second memory unit and the fourth memory unit.
13. The semiconductor memory device according to claim 12 , further comprising:
a third line connected to the first memory unit and the third memory unit, the third line and the first line being stacked in a first direction, the first direction crossing the substrate; and
a fourth line connected to the second memory unit and the fourth memory unit, the fourth line and the second line being stacked in the first direction.
14. A semiconductor memory device, comprising:
a first memory unit including a first memory cell and a second memory cell stacked in a first direction;
a second memory unit including a third memory cell and a fourth memory cell stacked in the first direction, the second memory unit being provided separately from the first memory unit in a second direction, the second direction being perpendicular to the first direction;
a first bit line extending in the second direction, the first bit line being provided above the first memory unit and the second memory unit;
a second bit line extending in the second direction, the second bit line being provided above the first memory unit and the second memory unit and adjacent to the first bit line in a third direction, the third direction being perpendicular to the first direction and the second direction;
a first contact connected to the first bit line and the first memory unit;
a second contact connected to the second bit line and the second memory unit, the second contact being provided separately from the first contact in the second direction and the third direction; and
a first conductive layer connected to a gate of the first memory cell, and a gate of the third memory cell.
15. The semiconductor memory device according to claim 14 further comprising:
a third memory unit including a fifth memory cell and a sixth memory cell stacked in the first direction, the third memory unit being provided separately from the first memory unit in the third direction;
a fourth memory unit including a seventh memory cell and an eighth memory cell stacked in the first direction, the fourth memory unit being provided separately from the third memory unit in the second direction;
a third bit line extending in the second direction, the third bit line being provided above the third memory unit and the fourth memory unit and adjacent to the second bit line in the third direction;
a fourth bit line extending in the second direction, the fourth bit line being provided above the third memory unit and the fourth memory unit and adjacent to the third bit line in the third direction;
a third contact connected to the third bit line and the third memory unit;
a fourth contact connected to the fourth bit line and the fourth memory unit, the fourth contact being provided separately from the third contact in the second direction and the third direction; and
a second conductive layer connected to a gate of the fifth memory cell, and a gate of the seventh memory cell.