Semiconductor device and manufacturing method thereof
A semiconductor device includes a first interlayer dielectric (ILD) layer disposed over a substrate, and a first metal wiring pattern formed in the first interlayer dielectric layer and extending in a first direction parallel with the substrate. In a cross section along a second direction which crosses the first direction and is in parallel with the substrate, a top of the first metal wiring pattern is covered by a first two-dimensional material layer.
1. A semiconductor device, comprising:
a first interlayer dielectric (ILD) layer disposed over a substrate;
a first metal wiring pattern formed in the first interlayer dielectric layer and extending in a first direction parallel with the substrate;
a second ILD layer disposed over the first ILD layer and the first metal wiring pattern; and
a second metal wiring pattern formed in the second ILD layer and connected to the first metal wiring pattern, wherein:
in a cross section along a second direction which crosses the first direction and is in parallel with the substrate, a top of the first metal wiring pattern is at least partially covered by a first two-dimensional material layer,
in the cross section, sides and bottom of the first metal wiring pattern are covered by a second two-dimensional material layer,
the first and second two-dimensional material layers are single layers of two-dimensional material,
the first two-dimensional material layer and the second two-dimensional material layer are different materials,
the first two-dimensional material layer is disposed only over the first metal wiring pattern, and
the second metal wiring pattern passes through the first two-dimensional material layer and is in direct contact with a surface of the first metal wiring pattern.
2. The semiconductor device of claim 1 wherein the first and second metal wiring patterns include Cu, and the second metal wiring pattern passing through the first two-dimensional material layer is in direct contact with a Cu surface of the first metal wiring pattern.
3. The semiconductor device of claim 1 , wherein the first two-dimensional material layer and the second two-dimensional material layer include graphene, a transition metal dichalcogenide (TMD), or BN.
4. The semiconductor device of claim 3 , wherein the TMD includes one of MoS 2 , WS 2 and NbSe 2 .
5. A semiconductor device, comprising:
a first interlayer dielectric (ILD) layer disposed over a substrate;
a first metal wiring pattern formed in the first interlayer dielectric layer and extending in a first direction parallel with the substrate,
wherein the first metal wiring pattern includes a first lower portion and a first upper portion;
a second ILD layer disposed over the first ILD layer and the first metal wiring pattern; and
a second metal wiring pattern formed in the second ILD layer and connected to the first metal wiring pattern,
wherein the second metal wiring pattern includes a second lower portion and a second upper portion,
in a cross section along a second direction, which crosses the first direction and is in parallel with the substrate, a top of the second metal wiring pattern is fully covered by a first two-dimensional material layer,
the first two-dimensional material layer is a single layer of two-dimensional material, and
the first two-dimensional material layer is in direct contact with a surface of the second metal wiring pattern,
wherein in the cross section, sides and bottom of the upper portion of the second metal wiring pattern are covered by a second two-dimensional material layer,
in the cross section, a part of a top of the first metal wiring pattern is covered by a third two-dimensional material layer, and the second metal wiring pattern passes through the third two-dimensional material layer and is in direct contact with a surface of the first metal wiring pattern,
in the cross section, sides and bottom of the upper portion of the first metal wiring pattern are covered by a fourth two-dimensional material layer, and
wherein the first two-dimensional material layer and the second two-dimensional material layer are different materials.
6. The semiconductor device of claim 5 , wherein the first two-dimensional material layer covering the top of the second metal wiring pattern only covers the second metal wiring pattern.
7. The semiconductor device of claim 5 , wherein the third two-dimensional material layer covering the top of the first metal wiring pattern only covers the first metal wiring pattern.
8. The semiconductor device of claim 5 , wherein:
the first and second metal wiring patterns include Cu, and
the first two-dimensional material layer is in direct contact with a Cu surface of the second metal wiring pattern.
9. The semiconductor device of claim 5 , wherein the lower portion of the second metal wiring pattern is in direct contact with a Cu surface of the first metal wiring pattern.
10. The semiconductor device of claim 5 , wherein the third two-dimensional material layer and the fourth two-dimensional material layer include a same material.
11. The semiconductor device of claim 5 , wherein the third two-dimensional material layer and the fourth two-dimensional material layer are different materials.
12. A method of manufacturing a semiconductor device, comprising:
forming a first interlayer dielectric layer over a substrate;
forming a first recess in the first interlayer dielectric layer;
forming a first conductive material layer in a lower portion of the first recess;
forming a single layer of a first two-dimensional material layer over the first conductive material layer and sidewalls of the first recess above the first conductive material layer;
forming a first metal layer in the first recess over the first two-dimensional material layer;
forming a single layer of a second two-dimensional material layer over the first metal layer;
forming a second interlayer dielectric layer over the second two-dimensional material layer and the first interlayer dielectric layer;
forming a second recess in the second interlayer dielectric layer exposing the second two-dimensional material layer;
forming a second conductive material layer in a lower portion of the second recess;
forming a single layer of a third two-dimensional material layer over the second conductive material layer and sidewalls of the second recess above the second conductive material layer;
forming a second metal layer in the second recess over the third two-dimensional material layer; and
forming a single layer of a fourth two-dimensional material layer over the second metal layer.
13. The method according to claim 12 , further comprising removing a metal oxide layer on an upper surface of the first metal wiring pattern before forming the second two-dimensional material layer,
wherein the metal oxide layer is a metal oxide of the first metal wiring pattern.
14. The method according to claim 12 , further comprising partially removing the second two-dimensional material layer to expose an upper surface of the first metal wiring pattern before forming the second conductive material layer.
15. The method according to claim 12 , wherein the fourth two-dimensional material layer covering the top of the second metal wiring pattern only covers the second metal wiring pattern.
16. The method according to claim 12 , wherein the first two-dimensional material layer and the second two-dimensional layer are different materials.
17. The semiconductor device of claim 1 , wherein the first ILD layer is made of a low-k material having a dielectric constant k lower than 3.5.
18. The semiconductor device of claim 1 , wherein the first ILD layer is made of a low-k material having a dielectric constant k lower than 2.5.
19. The semiconductor device of claim 1 , wherein the first ILD layer is made of one or more layers of a carbon-containing material, organosilicate glass, a porogen-containing material, or combinations thereof.
20. The semiconductor device of claim 1 , wherein the first ILD layer comprises one or more selected from the group consisting of a silicon oxide, silicon nitride, SiON, SiOC, SiOCN, and SiCOH.