IP Library Granted Patent US 10,714,586
Granted Patent B2
US 10,714,586 · App. 16/049,589 · Granted Jul 14, 2020

Semiconductor device and a method for fabricating the same

Inventors: Chia-Ming Hsu (Hualien County, TW); Pei-Yu Chou (Hsinchu County, TW); Chih-Pin Tsao (Zhubei, TW); Kuang-Yuan Hsu (Taichung, TW); Jyh-Huei Chen (Hsinchu, TW)
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
H01L29/45H01L21/32053H01L21/76802H01L21/76832H01L21/76834H01L21/76849H01L21/76867H01L21/76877H01L21/76889H01L21/76897H01L21/823418H01L23/485H01L23/53209H01L23/53238H01L23/53266H01L27/0886H01L29/41791H01L29/665H01L29/66795H01L21/0214H01L21/0217H01L21/02167H01L21/28518H01L21/76805H01L21/76843H01L21/76855H01L29/7848
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Quick Facts
Patent No.
US 10,714,586
App. No.
16/049,589
Granted
Jul 14, 2020
Kind
B2
Abstract

A semiconductor device includes a source/drain region, a source/drain silicide layer formed on the source/drain region, and a first contact disposed over the source/drain silicide layer. The first contact includes a first metal layer, an upper surface of the first metal layer is at least covered by a silicide layer, and the silicide layer includes a same metal element as the first metal layer.

Claims (50)

1. A semiconductor device including a field effect transistor, comprising:

a source/drain region;

a source/drain silicide layer formed on the source/drain region;

an interlayer dielectric layer;

a first contact disposed in the interlayer dielectric layer over the source/drain silicide layer; and

a second contact disposed over the first contact, wherein:

the first contact includes a first metal layer and an adhesive layer disposed between the first metal layer and the interlayer dielectric layer,

an upper surface of the first metal layer is covered by a silicide layer,

a side face of the silicide layer is covered by the adhesive layer,

the silicide layer includes a same metal element as the first metal layer, and

the second contact partially penetrates in the silicide layer such that a bottom of the second contact is located at a middle of the silicide layer.

2. The semiconductor device of claim 1 , wherein:

the adhesive layer is disposed between the first metal layer and the source/drain silicide layer.

3. The semiconductor device of claim 1 ,

wherein the silicide layer protrudes above an upper surface of the interlayer dielectric layer.

4. The semiconductor device of claim 1 , wherein the silicide layer is made of Co silicide and the first metal layer is made of Co.

5. The semiconductor device of claim 1 , further comprising:

an insulating layer in contact with an upper surface of the silicide layer and the dielectric layer,

wherein the insulating layer is made of a different material than the dielectric layer.

6. The semiconductor device of claim 5 , wherein the insulating layer includes at least one selected from the group consisting of SiN, SiC, SiCN and SiON.

7. A semiconductor device including a field effect transistor, comprising:

a first interlayer dielectric layer;

a first contact embedded in the first interlayer dielectric layer and disposed over a underlying conductive layer;

an adhesive layer disposed between the first contact and the underlying conductive layer;

a first silicide layer covering an upper surface of the first metal layer;

an insulating layer disposed over the first interlayer dielectric layer;

a second interlayer dielectric layer disposed over the insulating layer; and

a second contact embedded in the first interlayer dielectric layer and in contact with at least one of the silicide layer and the first contact, wherein:

the silicide layer includes a same metal element as the first metal layer,

a side face of the silicide layer is covered by the adhesive layer, and

the second contact passes through the insulating layer and partially penetrates in the silicide layer such that a bottom of the second contact is located at a middle of the silicide layer.

8. The semiconductor layer of claim 7 , wherein the second contact passes through the insulating layer and is in contact with an upper surface of the silicide layer.

9. The semiconductor layer of claim 7 , wherein the silicide layer covers an entirely of an upper surface of the first contact.

10. The semiconductor device of claim 7 , wherein the silicide layer is made of Co silicide and the first metal layer is made of Co.

11. The semiconductor device of claim 7 , wherein:

the insulating layer covers an upper surface of the silicide layer and the first interlayer dielectric layer, and

the insulating layer is made of a different material than the first and second interlayer dielectric layers.

12. The semiconductor device of claim 11 , wherein the insulating layer includes at least one selected from the group consisting of SiN, SiC, SiCN and SiON.

13. A semiconductor device including a field effect transistor, comprising:

a first contact disposed over a conductive portion formed over a substrate and embedded in an inter layer dielectric layer;

an adhesive layer disposed between the interlayer dielectric layer and the first contact; and

a second contact disposed over the first contact, wherein:

the first contact includes a first metal layer,

an upper surface of the first metal layer is covered by a silicide layer,

a side face of the silicide layer is covered by the adhesive layer,

the silicide layer includes a same metal element as the first metal layer, and

the second contact partially penetrates in the silicide layer such that a bottom of the second contact is located at a middle of the silicide layer.

14. The semiconductor device of claim 13 , wherein the adhesive layer includes a TiN layer formed on a Ti layer.

15. The semiconductor device of claim 13 , wherein the adhesive layer cover side faces of the silicide layer.

16. The semiconductor device of claim 13 , wherein the silicide layer is made of Co silicide and the first metal layer is made of Co.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 6, 2019
From: HSU, CHIA-MING; TSAO, CHIH-PIN; CHEN, JYH-HUEI; HSU, KUANG-YUAN; CHOU, PEI-YU
To: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Reel/Frame 050288/0189 →
Continuity (3)
Division 15378574 · Dec 14, 2016
Provisional Application 62289148 · Jan 29, 2016
Related Publication 20180337244A1 · Nov 22, 2018
Cited By (1)
US 12,477,807