Display device having a rise timing of a gate-on voltage that differs from a rise timing of a first pulse signal
A display apparatus includes an image display region having pixels sectioned by scanning signal lines and video signal lines, scanning connecting lines, thin film transistors, selection signal lines connected to gate electrodes of the thin film transistors, plural ones of the thin film transistors connected to different ones of the scanning connecting lines being connected to one of the selection signal lines; and a scanning signal drive circuit. The scanning signal drive circuit performs a normal scanning mode in which pulse signals are supplied in turn to plural ones of the scanning connecting lines connected to the one of the selection signal lines, and in the normal scanning mode, a fall timing of the gate-on voltage differs from a fall timing of a last one of the pulse signals supplied to the plural ones of the scanning connecting lines during the selection period.
1. A display apparatus comprising:
an image display region having a plurality of pixels sectioned by a plurality of scanning signal lines and a plurality of video signal lines; and
outside regions disposed outside of the image display region,
the outside region comprising:
a plurality of scanning connecting lines connected to the scanning signal lines, plural ones of the scanning signal lines being connected to one of the scanning connecting lines;
a plurality of thin film transistors including first thin film transistors, a source electrode and a drain electrode of each of the first thin film transistors being connected to a corresponding one of the scanning signal lines and a corresponding one of the scanning connecting lines;
a plurality of selection signal lines connected to gate electrodes of the first thin film transistors, plural ones of the first thin film transistors connected to different ones of the scanning connecting lines being connected to one of the selection signal lines; and
a scanning signal drive circuit connected to the scanning connecting lines and the selection signal lines, wherein
the scanning signal drive circuit performs a normal scanning mode in which pulse signals are supplied in turn to plural ones of the plurality of scanning connecting lines connected to the one of the plurality of selection signal lines, during a selection period in which a gate-on voltage is applied to one of the plurality of selection signal lines, gate-off voltages are applied to other ones of the plurality of selection signal lines, and
in the normal scanning mode, a rise timing of the gate-on voltage differs from a rise timing of a first one of the pulse signals supplied to the plural ones of the plurality of scanning connecting lines during the selection period.
2. The display apparatus according to claim 1 , wherein the first one of the pulse signals rises after the gate-on voltage rises.
3. The display apparatus according to claim 1 , wherein
the scanning signal drive circuit:
generates a first clock signal and a second clock signal having a same cycle as the first clock signal and having rise and fall timings different from those of the first clock signal; and
controls rise and fall of the gate-on voltage based on the first clock signal, and controls rise and fall of the pulse signals based on the second clock signal.