FinFET device and method of forming and monitoring quality of the same
A FinFET structure with a gate structure having two notch features therein and a method of forming the same is disclosed. The FinFET notch features ensure that sufficient spacing is provided between the gate structure and source/drain regions of the FinFET to avoid inadvertent shorting of the gate structure to the source/drain regions. Gate structures of different sizes (e.g., different gate widths) and of different pattern densities can be provided on a same substrate and avoid inadvertent of shorting the gate to the source/drain regions through application of the notched features.
1. A FinFET device, the FinFET device comprising:
a fin supported by a substrate; and
a gate structure having two notch features individually in a first portion over the fin and a second portion overlapped with and extending along sidewalls of the fin, wherein a profile of the two notch features comprises:
a first width at a top surface of the first portion;
a second width at a top surface of the second portion;
a third width at a middle position of the second portion;
a fourth width at a bottom surface of the second portion;
a first height from the first width to the second width;
a second height from the second width to the fourth width; and
a third height from the third width to the fourth width, wherein the third width is smaller than the second width and a difference between the third width and the second width is in a range between 0.001 nm and 25 nm; and the second height is in a range between 0.001 nm and 25 nm; and
a second gate structure having two notch features individually in a third portion over the fin and a fourth portion overlapped with the sidewalls of the fin, the two notch features of the second gate structure being wherein the second gate structure defines a second channel length greater than the first channel length of the gate structure;
wherein the gate structure and the second gate structure have the same profile when viewed from a direction perpendicular to the first channel length, and further wherein a difference between the first width and the second width of the gate structure is equal to a difference between the first width and the second width of the second gate structure.
2. The FinFET device of claim 1 , wherein the first height is larger than combined height of the second height and the third height.
3. The FinFET device of claim 1 , wherein the third height is in a range between 0.001 nm and 25 nm.
4. The FinFET device of claim 1 , wherein the first width is larger than the second width.
5. The FinFET device of claim 1 , wherein the gate structure comprises a gate oxide layer and a gate electrode.
6. The FinFET device of claim 5 , wherein the gate oxide layer comprises a material selected from a group consisted of hafnium oxide, titanium nitride, silicon dioxide, silicon nitride, silicon oxynitride, and a combination thereof.
7. The FinFET device of claim 5 , wherein the gate electrode comprises a material selected from a group consisted of polycrystalline-silicon (poly-Si), poly-crystalline silicon germanium (poly-SiGe), silicon nitride, and a combination thereof.
8. The FinFET device of claim 1 , further comprising a hard mask on the gate structure.
9. The FinFET device of claim 8 , wherein the hard mask comprises a material selected from a group consisted of SiC, SiCN, SiN, TaO, TiO 2 , SiO 2 , Si 3 N 4 , SiON, and a combination thereof.
10. The FinFET device of claim 8 , wherein the hard mask comprises a two layer structure.
11. The FinFET device of claim 1 , further comprising:
the gate structure having a longitudinal axis extending in a first direction;
a second gate structure having a longitudinal axis extending in the first direction and being aligned with the first fin in the first direction, the second gate structure extending over the plurality of second fins and having portions overlapped with and extending along respective sidewalls of the plurality of second fins, wherein a profile of the second gate structure viewed from the first direction is the same as the profile of the gate structure viewed from the first direction; and
wherein an end of the gate structure viewed from a second direction perpendicular to the first direction is vertical, and a second end of the second gate structure viewed from the second direction is vertical.
12. The FinFET device of claim 1 , further comprising:
a third gate structure having two notch features individually in a fifth portion over the fin and a sixth portion overlapped with the sidewalls of the fin, wherein the third gate structure defines a third channel length greater than the second channel length; and
wherein the gate structure and the third gate structure are geometrically similar, and further wherein a difference between the first width and the second width of the gate structure is equal to a difference between the first width and the second width of the third gate structure.
13. A FinFET device, the FinFET device comprising:
a fin supported by a substrate; and
a first gate structure having two notch features individually in a first portion over the fin and a second portion extending along and overlapped with sidewalls of the fin, wherein a profile of the two notch features comprises:
a first width at a top surface of the first portion;
a second width at a top surface of the second portion;
a third width at a middle position of the second portion;
a fourth width at a bottom surface of the second portion;
a first height from the first width to the second width;
a second height from the second width to the fourth width; and
a third height from the third width to the fourth width, wherein the third width is smaller than the second width and a difference between the third width and the second width is in a range between 0.001 nm and 15 nm; and the second height is in a range between 0.001 nm and 50 nm, and further wherein the third height is about half the second height;
a second gate structure having two notch features individually in a third portion over the fin and a fourth portion overlapped with the sidewalls of the fin, the two notch features of the second gate structure being wherein the second gate structure defines a second channel length greater than the first channel length of the gate structure;
a third gate structure having two notch features individually in a fifth portion over the fin and a sixth portion overlapped with the sidewalls of the fin, wherein the third gate structure defines a third channel length greater than the second channel length; and
wherein the gate structure, the second gate structure and the third gate structure are geometrically similar, and further wherein a difference between the first width and the second width of the gate structure is equal to a difference between the first width and the second width of the second gate structure, and difference between the first width and the second width of the second gate structure is equal to a difference between the first width and the second width of the third gate structure.
14. The FinFET device of claim 11 , wherein the first gate structure extends along a first longitudinal axis and further wherein the gate structure is divided into at least two sections, the first section overlapping a first quantity of fins and the second section overlapping a second quantity of fins, the second quantity being greater than the first quantity.
15. The FinFET device of claim 11 , wherein the first gate structure has a slope, the slope being a ratio of the third height to the difference between the second width and the third width, and wherein the slope is in a range of between 0.067 and 25.
16. The FinFET device of claim 11 , wherein the first height is larger than combined height of the second height and the third height.
17. The FinFET device of claim 11 , wherein the first width is larger than the second width.
18. The FinFET device of claim 11 , further comprising:
an epitaxial source/drain region in the fin, the epitaxial source/drain having a topmost portion that is separated from the gate structure by a first distance and having a middle portion that is separated from the gate structure by a second distance that is less than the first distance; and
wherein the gate structure sidewall has a slope that causes the first distance and the second distance to be greater than the first distance and the second distance would otherwise be in the absence of the slope.
19. A FinFET device comprising:
a plurality of fins extending in a first longitudinal direction;
a gate structure extending in a second longitudinal direction perpendicular to the first longitudinal direction, the gate structure having a notched profile when viewed in cross-section along the first longitudinal direction, the notched profile including:
a first portion extending above at least one fin top surface, the first portion having a sidewall that slopes from a first width W 1 at a top height at a distance H 1 above the second portion, to a second width W 2 at a bottom height; and
a second portion extending along a sidewall of the at least one fin, the second portion having a sidewall that slopes from the second width W 2 at the top of the second portion to a third width W 3 at a point a first distance H 3 below the top of the second portion to a fourth width W 4 at a point a second distance H 2 below the top of the second portion, and wherein the top height of the first portion is a distance H 1 above the top of the second portion; and
wherein the following conditions are met by the profile of the gate structure:
W 1> W 2> W 3,
H 1> H 2,
H 3= H 2/2, and
0.067< H 3/( W 2− W 3)<25; and
a second gate structure extending parallel to the gate structure, the second gate structure defining a second channel length greater than the first channel length of the gate structure, and wherein the above conditions are met by the profile of the second gate structure.
20. The FinFET device of claim 19 , wherein H 2 is in a range between about 0.001 nm and about 50 nm.
21. The FinFET device of claim 19 , wherein W 3 >W 4 .