Fan-out semiconductor package

1. A fan-out semiconductor package comprising:

a frame including a plurality of insulating layers, a plurality of wiring layers disposed on the plurality of insulating layers, and a plurality of connection via layers penetrating through the plurality of insulating layers and electrically connecting the plurality of wiring layers to each other, and having a recess portion and a stopper layer disposed on a bottom surface of the recess portion;

a semiconductor chip including a body having an active surface having connection pads disposed thereon and an inactive surface opposing the active surface and a passivation layer disposed on the active surface and having openings exposing at least portions of the connection pads, and disposed in the recess portion so that the inactive surface is connected to the stopper layer;

a resin layer disposed on the active surface of the semiconductor chip;

an encapsulant covering at least portions of side surfaces of each of the semiconductor chip and the resin layer and filling at least portions of the recess portion;

a first redistribution layer disposed on the resin layer and the encapsulant;

first redistribution vias penetrating through the resin layer to fill via holes in the resin layer exposing at least portions of the connection pads and electrically connecting the connection pads and the first redistribution layer to each other; and

a connection member disposed on the resin layer and the encapsulant and including one or more second redistribution layers electrically connected to the first redistribution layer,

wherein the connection pads are electrically connected to the plurality of wiring layers.

2. The fan-out semiconductor package of claim 1 , wherein an upper surface of the resin layer and an upper surface of the encapsulant are coplanar with each other.

3. The fan-out semiconductor package of claim 2 , wherein an upper surface of an uppermost wiring layer of the plurality of wiring layers is coplanar with the upper surface of the resin layer and the upper surface of the encapsulant, and

at least portions of the first redistribution layer are in physical contact with at least portions of the uppermost wiring layer of the plurality of wiring layers.

4. The fan-out semiconductor package of claim 2 , wherein an upper surface of an uppermost connection via layer of the plurality of connection via layers is coplanar with the upper surface of the resin layer and the upper surface of the encapsulant, and

at least portions of the first redistribution layer are in physical contact with at least portions of the uppermost connection via layer of the plurality of connection via layers.

5. The fan-out semiconductor package of claim 1 , wherein the resin layer includes a photoimagable dielectric (PID).

6. The fan-out semiconductor package of claim 1 , wherein the plurality of insulating layers include a core insulating layer, one or more first build-up insulating layers disposed on a lower surface of the core insulating layer, and one or more second build-up insulating layers disposed on an upper surface of the core insulating layer, and

the core insulating layer has a thickness greater than that of each of the first and second build-up insulating layers.

7. The fan-out semiconductor package of claim 6 , wherein the number of the first build-up insulating layers and the number of the second build-up insulating layers are the same as each other.

8. The fan-out semiconductor package of claim 6 , wherein the recess portion penetrates through at least the core insulating layer and penetrates through at least one of the one or more first and second build-up insulating layers.

9. The fan-out semiconductor package of claim 6 , wherein first connection vias penetrating through the first build-up insulating layer and second connection vias penetrating through the second build-up insulating layer are tapered in opposite directions to each other.

10. The fan-out semiconductor package of claim 6 , wherein the recess portion does not penetrate through at least one of the first build-up insulating layers.

11. The fan-out semiconductor package of claim 1 , wherein the stopper layer is a metal layer.

12. The fan-out semiconductor package of claim 11 , wherein at least one of the plurality of wiring layers includes a ground, and

the metal layer is electrically connected to the ground.

13. The fan-out semiconductor package of claim 1 , wherein the inactive surface of the semiconductor chip is attached to the stopper layer through an adhesive member.

14. The fan-out semiconductor package of claim 1 , wherein walls of the recess portion are tapered.

15. The fan-out semiconductor package of claim 1 , wherein the stopper layer has a planar area greater than that of the inactive surface of the semiconductor chip.

16. The fan-out semiconductor package of claim 1 , wherein the bottom surface of the recess portion has a planar area greater than that of the inactive surface of the semiconductor chip.

17. The fan-out semiconductor package of claim 1 , wherein a region of the stopper layer exposed by the recess portion has a thickness smaller than that of an edge region of the stopper layer that is not exposed by the recess portion.

18. The fan-out semiconductor package of claim 1 , wherein the edge region of the stopper layer that is not exposed by the recess portion is disposed between two of the plurality of insulating layers.

19. The fan-out semiconductor package of claim 1 , further comprising:

a first passivation layer disposed on the connection member and having openings exposing at least portions of an uppermost second redistribution layer of the second redistribution layers;

underbump metal layers disposed in the openings of the first passivation layer and connected to at least portions of the exposed second redistribution layer; and

electrical connection structures disposed on the first passivation layer and connected to the underbump metal layers.

20. The fan-out semiconductor package of claim 1 , further comprising a second passivation layer disposed beneath the frame and having openings exposing at least portions of a lowermost wiring layer of the plurality of wiring layers.