Bond-over-active circuity gallium nitride devices
Implementations of semiconductor devices may include: a first layer with a plurality of cells, each cell having a drain finger, a source finger and a gate ring; a second layer having a drain pad and a source pad, the drain pad having a width and a source pad having a width substantially the same as the drain pad; wherein a width of each drain finger of the first layer is wider than a width of each source finger of the first layer; and wherein each drain pad is coupled to each drain finger through a first contact and the source pad is coupled to each source finger through a second contact, where a width of the first contact is wider than a width of the second contact.
1. A semiconductor device comprising:
a first layer with a plurality of cells, each cell comprising a drain finger, a source finger and a gate ring; and
a second layer comprising a drain pad and a source pad, the drain pad having a width and a source pad having a width substantially the same as the drain pad;
wherein a width of each drain finger of the first layer is wider than a width of each source finger of the first layer;
wherein each drain pad is coupled to each drain finger through a first contact and the source pad is coupled to each source finger through a second contact, where a width of the first contact is wider than a width of the second contact; and
wherein one of the drain pad or the source pad is positioned over one of the drain finger or the source finger.
2. The semiconductor device of claim 1 , wherein the plurality of cells are gallium nitride (GaN) high electron mobility transistors (HEMT).
3. A semiconductor device comprising:
a first cell comprising a first plurality of fingers and a second cell comprising a second plurality of fingers;
a first drain pad coupled to the first plurality of fingers;
a second drain pad coupled to the second plurality of fingers;
a source pad coupled to the first plurality of fingers and the second plurality of fingers;
a gate bus located between the first plurality of fingers and the second plurality of fingers; and
at least one gate pad coupled to the gate bus;
wherein one of the first drain pad, the second drain pad, the source pad, or the gate pad is positioned over one of the first plurality of fingers, the second plurality of fingers, or the gate bus.
4. The semiconductor device of claim 3 , further comprising a second gate pad coupled to the gate pad on an end of the gate bus opposing an end to which the at least one gate pad is coupled.
5. The semiconductor device of claim 3 , wherein the source pad is coupled to a substrate of a second transistor forming a cascode device.
6. The semiconductor of claim 5 , wherein the second transistor is a silicon metal-oxide semiconductor field effect transistor (Si-MOSFET) having a Si substrate.
7. The semiconductor of claim 6 , wherein the Si substrate of the Si-MOSFET is coupled to a conductive film and the conductive film is coupled to a drain of the Si-MOSFET.
8. The semiconductor device of claim 5 , wherein gate vias are used to couple the source pad to the second transistor.
9. The semiconductor device of claim 5 , wherein the gate bus and the gate pad are covered by a passivation layer and the source pads and the drain pads are open through the passivation layer.
10. A semiconductor device comprising:
a first cell comprising a first plurality of fingers and a second cell comprising a second plurality of fingers;
a first drain pad coupled over the first plurality of fingers;
a second drain pad coupled over the second plurality of fingers;
a source pad coupled over the first plurality of fingers and the second plurality of fingers;
a gate bus located between the first plurality of fingers and the second plurality of fingers; and
at least one gate pad coupled over the gate bus.