Programmable multiply-add array hardware
An integrated circuit including a data architecture including N adders and N multipliers configured to receive operands. The data architecture receives instructions for selecting a data flow between the N multipliers and the N adders of the data architecture. The selected data flow includes the options: (1) a first data flow using the N multipliers and the N adders to provide a multiply-accumulate mode and (2) a second data flow to provide a multiply-reduce mode.
1. A method for specifying functionalities to be performed on a data architecture including N adders and N multipliers configured to receive operands, the method comprising:
receiving instructions for the data architecture to operate in one of a multiply-reduce mode or a multiply-accumulate mode, wherein the N multipliers and at least some of the N adders of the data architecture are used both in the multiply-reduce mode and the multiply-accumulate mode; and
selecting, based on the instructions, a data flow between the N multipliers and the at least some of the N adders of the data architecture,
wherein the N multipliers includes a first multiplier of which output data is provided to a first adder among the at least some of the N adders in the multiply-reduce mode and to a second adder among the at least some of the N adders in the multiply-accumulate mode.
2. The method of claim 1 , wherein selecting the data flow includes, in response to receiving instructions corresponding to the multiply-reduce mode, selecting a first data flow using the N multipliers and N−1 adders, wherein one of the N adders is not used.
3. The method of claim 2 , wherein the first data flow comprises the N−1 adders receiving input resulting from the N multipliers.
4. The method of claim 1 , wherein selecting the data flow includes, in response to receiving instructions corresponding to the multiply-accumulate mode, selecting a second data flow using the N multipliers and the N adders.
5. The method of claim 4 , wherein the second data flow comprises each adder of the N adders receiving an input operand from a corresponding multiplier of the N multipliers.
6. An integrated circuit comprising:
a data architecture including N adders and N multipliers configured to receive operands, wherein the data architecture receives instructions for selecting a data flow between the N multipliers and at least some of the N adders of the data architecture, the selected data flow including the options:
a first data flow using the N multipliers and the N adders to provide a multiply-accumulate mode; and
a second data flow to provide a multiply-reduce mode,
wherein the N multipliers and the at least some of the N adders are used both in the first data flow and the second data flow, and
wherein the N multipliers includes a first multiplier of which output data is provided to a first adder among the at least some of the N adders in the first data flow and to a second adder among the at least some of the N adders in the second data flow.
7. The integrated circuit of claim 6 , wherein the first data flow uses each adder of the N adders to receive an input operand from a corresponding multiplier of the N multipliers.
8. The integrated circuit of claim 6 , wherein the second data flow uses the N multipliers and N−1 adders, wherein one of the N adders is not used.
9. The integrated circuit of claim 8 , wherein the second data flow uses the N−1 adders to receive input resulting from the N multipliers.
10. A non-transitory computer-readable storage medium that stores a set of instructions that is executable by at least one processor of a device to cause the device to perform a method for specifying functionalities to be performed on a data architecture including N adders and N multipliers configured to receive operands, the method comprising:
receiving instructions for the data architecture to operate in one of a multiply-reduce mode or a multiply-accumulate mode, wherein the N multipliers and at least some of the N adders of the data architecture are used both in the multiply-reduce mode and the multiply-accumulate mode; and
selecting, based on the instructions, a data flow between the N multipliers and the at least some of the N adders of the data architecture,
wherein the N multipliers includes a first multiplier of which output data is provided to a first adder among the at least some of the N adders in the multiply-reduce mode and to a second adder among the at least some of the N adders in the multiply-accumulate mode.
11. The non-transitory computer-readable storage medium of claim 10 , wherein selecting the data flow includes, in response to receiving instructions corresponding to the multiply-reduce mode, selecting a first data flow using the N multipliers and N−1 adders, wherein one of the N adders is not used.
12. The non-transitory computer-readable storage medium of claim 11 , wherein the first data flow comprises the N−1 adders receiving input resulting from the N multipliers.
13. The non-transitory computer-readable storage medium of claim 10 , wherein selecting the data flow includes, in response to receiving instructions corresponding to the multiply-accumulate mode, selecting a second data flow using the N multipliers and the N adders.
14. The non-transitory computer-readable storage medium of claim 13 , wherein the second data flow comprises each adder of the N adders receiving an input operand from a corresponding multiplier of the N multipliers.