IP Library › Patent Application 16055170
Patent Application
App. No. 16/055,170

Configurable Computing Array Implementing Math Functions with Multiple Input Variables

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Quick Facts
Patent No.
US None
App. No.
16/055,170
Abstract

To implement a math function with multiple input variables, a configurable computing array comprises at least an array of configurable interconnects, an array of configurable logic elements, and an array of configurable computing elements. Each configurable computing element comprises at least a memory for storing a look-up table (LUT) for a math function with a single input variable.

Claims (30)

1 - 20 . (canceled)

21 . A configurable computing array, comprising:

at least an array of configurable interconnects including a configurable interconnect for selectively realizing an interconnect from an interconnect library; and

at least an array of configurable computing elements including a configurable computing element for realizing a selected one of a plurality of math functions;

wherein said configurable computing array realizes a math function with multiple input variables by programming said array of configurable interconnects and said array of configurable computing elements.

22 . The configurable computing array according to claim 21 , wherein said configurable computing element comprises at least a memory for storing a look-up table (LUT) for said selected math function.

23 . The configurable computing array according to claim 22 , wherein said memory is a three-dimensional memory.

24 . The configurable computing array according to claim 21 , wherein said array of configurable computing elements further comprises another configurable computing element for realizing another selected one of said plurality of math functions.

25 . The configurable computing array according to claim 21 , wherein said array of configurable interconnects and said array of configurable computing elements are disposed on different surfaces.

26 . The configurable computing array according to claim 21 , further comprising at least an array of configurable logic elements including a configurable logic element for selectively realizing a logic function from a logic library.

27 . The configurable computing array according to claim 21 , further comprising at least one multiplier.

28 . A configurable computing array, comprising:

at least an array of configurable interconnects including a configurable interconnect, wherein said configurable interconnect selectively realizes an interconnect from an interconnect library; and

at least an array of configurable computing elements including a configurable computing element, wherein said configurable computing element comprises at least a memory for storing a look-up table (LUT) for a math function with a single input variable;

wherein said configurable computing array realizes a math function with multiple input variables by programming said array of configurable interconnects and said array of configurable computing elements.

29 . The configurable computing array according to claim 28 , further comprising at least another memory for storing another LUT for another math function with another single input variable.

30 . The configurable computing array according to claim 28 , wherein said array of configurable interconnects and said array of configurable computing elements are disposed on different surfaces.

31 . The configurable computing array according to claim 28 , wherein said memory is a three-dimensional memory.

32 . The configurable computing array according to claim 28 , further comprising at least an array of configurable logic elements including a configurable logic element, wherein said configurable logic element selectively realizes a logic function from a logic library.

33 . The configurable computing array according to claim 28 , further comprising at least one multiplier.

34 . A configurable computing array, comprising:

at least an array of configurable interconnects including a configurable interconnect, wherein said configurable interconnect selectively realizes an interconnect from an interconnect library; and

at least an array of configurable computing elements including a configurable computing element, wherein said configurable computing element can be re-configured to realize different math functions;

wherein said configurable computing array realizes a math function with multiple input variables by programming said array of configurable interconnects and said array of configurable computing elements.

35 . The configurable computing array according to claim 34 , wherein said configurable computing element comprises at least a re-programmable memory for storing a look-up table (LUT) for at least a math function.

36 . The configurable computing array according to claim 35 , wherein said re-programmable memory is loaded with a first LUT for a first math function during a first usage cycle and loaded with a second LUT for a second math function during a second usage cycle.

37 . The configurable computing array according to claim 35 , wherein said re-programmable memory is a three-dimensional writable memory.

38 . The configurable computing array according to claim 34 , wherein said array of configurable interconnects and said array of configurable computing elements are disposed on different surfaces.

39 . The configurable computing array according to claim 34 , further comprising at least an array of configurable logic elements including a configurable logic element, wherein said configurable logic element selectively realizes a logic function from a logic library.

40 . The configurable computing array according to claim 34 , further comprising at least one multiplier.