Semiconductor package
A semiconductor package includes a bottom package having a lower substrate and a lower semiconductor chip mounted on the lower substrate, an interposer substrate on the bottom package, a first top package and a second top package that are mounted on the interposer substrate, and a heat spreader that is interposed between the first top package and the second top package and separates the first and second top packages from each other. The heat spreader is adhered to the interposer substrate through a plurality of first connection terminals.
1. A semiconductor package, comprising:
a bottom package including a lower package substrate and a lower semiconductor chip mounted on the lower package substrate;
an interposer on the bottom package;
a first top package and a second top package mounted on the interposer;
a heat spreader interposed between respective lateral surfaces of the first top package and the second top package, the heat spreader separating the first and second top packages from each other; and
a plurality of first connection terminals adhering the heat spreader to the interposer,
wherein the interposer comprises an interposer body having a top surface, and a first circuit pattern and a second circuit pattern on the interposer body,
the first and second top packages are coupled to the first circuit pattern,
the heat spreader is coupled to the second circuit pattern, and
the second circuit pattern is electrically insulated from the first circuit pattern in the semiconductor package and extends on the top surface of the interposer body from a central portion of the interposer body toward an outer peripheral portion of the interposer body.
2. The semiconductor package of claim 1 , wherein a top surface of the lower semiconductor chip contacts the interposer.
3. The semiconductor package of claim 1 , wherein the interposer has a ground circuit, and
the heat spreader is coupled to the interposer and electrically connected to the ground circuit of the interposer.
4. The semiconductor package of claim 1 , wherein the heat spreader comprises an extension segment extending over a top surface of the first top package and a top surface of the second top package.
5. The semiconductor package of claim 4 , further comprising a thermal transfer material layer interposed between the extension segment and the top surface of at least one of the first and second top packages.
6. The semiconductor package of claim 4 , wherein the heat spreader comprises a plurality of heat radiation fins that protrude above a top surface of the extension segment and extend longitudinally parallel to each other in one direction.
7. The semiconductor package of claim 4 , wherein the heat spreader comprises a plurality of protrusions protruding from the extension segment toward the top surface of the second top package.
8. The semiconductor package of claim 1 , wherein the heat spreader has a side wall segment disposed outward of and extending over outwardly facing lateral surfaces of the first top package and outwardly facing lateral surfaces of the second top package such that the heat spreader surrounds the lateral surfaces of the first top package and the lateral surfaces of the second top package.
9. The semiconductor package of claim 1 , wherein the lower package substrate is a redistribution substrate and the bottom package includes an interconnect substrate on the redistribution substrate, the interconnect substrate having a hole therethrough, and
the lower semiconductor chip is disposed on the redistribution substrate within the hole of the interconnect substrate.
10. The semiconductor package of claim 9 , wherein the bottom package has a conductive via in the interconnect substrate, and the interposer is electrically connected to the redistribution substrate by the conductive via.
11. The semiconductor package of claim 1 , further comprising a plurality of second connection terminals interposed between the lower package substrate and the interposer,
wherein the second connection terminals are disposed beside the lower semiconductor chip, and
the interposer is coupled to the lower package substrate by the plurality of second connection terminals.
12. The semiconductor package of claim 1 , wherein the second circuit pattern comprises:
a first part at the central portion of the interposer body and on which the heat spreader is mounted; and
a second part that radially extends from the first part.
13. A semiconductor package, comprising:
a bottom package including a lower package substrate and a semiconductor chip mounted on the lower package substrate;
an interposer on the bottom package, the interposer having a first region and a second region laterally spaced apart from each other;
a first top package on the first region of the interposer;
a second top package on the second region of the interposer; and
a heat spreader including a partition wall segment that separates the first and second top packages from each other, an extension segment covering top surfaces of the first and second top packages, and side wall segments surrounding lateral surfaces of the first and second top packages along edges of the interposer.
14. The semiconductor package of claim 13 , further comprising a plurality of connection terminals on the interposer,
wherein the heat spreader is adhered to the interposer through the plurality of connection terminals.
15. The semiconductor package of claim 14 , wherein the interposer has an interposer body and a ground circuit on the interposer body, and
the heat spreader is coupled to the ground circuit of the interposer.
16. The semiconductor package of claim 13 , further comprising a thermal transfer material layer interposed between the heat spreader and the first top package, and between the heat spreader and the second top package.
17. The semiconductor package of claim 13 , wherein the interposer comprises:
an interposer body;
a first circuit pattern on the interposer body and to which the first and second top packages are coupled; and
a second circuit pattern on the interposer body and electrically insulated from the first circuit pattern in the semiconductor package, and
the second circuit pattern extends from a central portion of the interposer body toward an outer peripheral portion of the interposer body when viewed in plan.
18. The semiconductor package of claim 17 , wherein a top surface of the semiconductor chip is in contact with the interposer.
19. The semiconductor package of claim 13 , wherein the extension segment comprises a plurality of heat radiation fins protruding upwardly from the extension segment and extending longitudinally parallel to each other in one direction.