Control of pulse generator in driving control device

1. A circuit for controlling a power converter, the circuit comprising:

a pulse generator configured to generate a first pulse signal and a second pulse signal in response to an input signal, the first pulse signal being asserted at least a given time interval after the input signal has been de-asserted, the pulse generator outputting a single pulse signal in each cycle of the input signal to turn on a first-side switching device;

a level-shift circuit configured to shift a level of the first pulse signal to generate a first shifted signal and to shift a level of the second pulse signal to generate a second shifted signal;

a logic circuit configured to control the first-side switching device in response to the first shifted signal and the second shifted signal; and

an output node configured to output an output signal,

wherein the first-side switching device is coupled to a second side-switching device at the output node, and the given time interval includes a first time interval when the output signal has a negative value, the given time interval being sufficiently long to avoid an overlap between the first time interval and an on-time duration of the first pulse signal.

2. The circuit of claim 1 , wherein the pulse generator asserts the first pulse signal at a first time when an off-time duration of the input signal is shorter than the given time interval, the first time being a time at which the given time interval elapses after the input signal has been de-asserted.

3. The circuit of claim 2 , wherein the pulse generator asserts the first pulse signal at a second time in response to an edge of the input signal when the off-time duration of the input signal is equal to or longer than the given time interval.

4. The circuit of claim 2 , wherein the pulse generator includes:

an off-duration ensuring circuit generating a modified input signal in response to a third pulse signal corresponding to an edge of the input signal; and

a first edge detector generating the first pulse signal in response to the modified input signal.

5. The circuit of claim 4 , wherein the off-duration ensuring circuit includes:

an off-duration timer de-asserting a detection signal in response to the third pulse signal and asserting the detection signal at a time at which the given time interval elapses after the detection signal has been de-asserted; and

a logic gate generating the modified input signal in response to the detection signal and the input signal.

6. The circuit of claim 5 , wherein the off-duration timer includes:

a resistor;

a latch circuit receiving the third pulse signal as a reset signal;

a first transistor having a source coupled to a power supply voltage, a gate coupled to the latch circuit, and a drain coupled to a first end of the resistor;

a second transistor having a source coupled to a ground, a gate receiving the detection signal, and a drain coupled to a second end of the resistor; and

a capacitor having a first end coupled to an input line of an inverter and a second end coupled to the ground.

7. The circuit of claim 5 , wherein the off-duration timer includes:

a current source;

a latch circuit receiving the third pulse signal as a reset signal;

a transistor having a source coupled to a ground, a gate receiving the detection signal, and a drain coupled to the current source; and

a capacitor having a first end coupled to an input line of an inverter and a second end coupled to the ground.

8. The circuit of claim 4 , wherein the pulse generator further includes:

a second edge detector generating the third pulse signal in response to an inverted version of the input signal.

9. The circuit of claim 1 , wherein the given time interval further includes a second time interval when the output signal is settled to have a non-negative value, the second time interval being determined to make an estimated percentage of an occurrence of a latch off failure equal to or less than 5%, 3%, 1%, 0.5%, 0.3%, 0.1%, or 0.01%.

10. The circuit of claim 1 , wherein the given time interval further includes a second time interval when the output signal is settled to have a non-negative value, the second time interval immediately following the first time interval and being equal to or shorter than 0.1%, 0.3%, 0.5%, 1%, 3%, 5%, 10%, 25%, or 50% of the first time interval.

11. The circuit of claim 1 , wherein the given time interval starts when the input signal is de-asserted.

12. A method of controlling a power converter, the method comprising:

generating a first pulse signal and a second pulse signal in response to an input signal, the first pulse signal being asserted at least a given time interval after the input signal has been de-asserted, the first pulse signal being a single pulse signal in each cycle of the input signal;

shifting a level of the first pulse signal to generate a first shifted signal and shifting a level of the second pulse signal to generate a second shifted signal;

controlling a first-side switching device in response to the first shifted signal and the second shifted signal; and

outputting an output signal at an output node,

wherein the first-side switching device and a second-side switching device are coupled to each other at the output node, and the given time interval includes a first time interval when the output signal has a negative value and a second time interval when the output signal is settled to have a non-negative value, the given time interval being sufficiently long to avoid an overlap between the first time interval and an on-time duration of the first pulse signal, the second time interval being determined to make an estimated percentage of an occurrence of a latch off failure equal to or less than 5%, 3%, 1%, 0.5%, 0.3%, 0.1%, or 0.01%.

13. The method of claim 12 , further comprising:

asserting the first pulse signal at a first time when an off-time duration of the input signal is shorter than the given time interval, the first time being a time at which the given time interval elapses after the input signal has been de-asserted.

14. The method of claim 13 , further comprising:

asserting the first pulse signal at a second time in response to an edge of the input signal when the off-time duration of the input signal is equal to or longer than the given time interval.

15. The circuit of claim 13 , further comprising:

generating a modified input signal in response to a third pulse signal corresponding to an edge of the input signal; and

generating the first pulse signal in response to the modified input signal.

16. The method of claim 15 , further comprising de-asserting a detection signal in response to the third pulse signal and asserting the detection signal at a time at which the given time interval elapses after the detection signal has been de-asserted,

wherein the modified input signal is generated in response to the detection signal and the input signal.

17. The method of claim 15 , further comprising:

generating the third pulse signal in response to an inverted version of the input signal.

18. A power converter comprising:

a first-side switching device;

a second-side switching device coupled to the first-side switching device at an output node, the output node outputting an output signal;

a controller configured to generate first and second input signals; and

a driving control device configured to generate a first control signal in response to the first input signal to control the first-side switching device and a second control signal in response to the second input signal to control the second-side switching device,

wherein the driving control device includes a pulse generator configured to generate a first pulse signal and a second pulse signal in response to the first input signal, the first pulse signal being asserted at least a given time interval after the first input signal has been de-asserted, the given time interval including a first time interval when the output signal has a negative value, the given time interval being sufficiently long to avoid an overlap between the first time interval and an on-time duration of the first pulse signal, the pulse generator being further configured to output a single pulse signal in each cycle of the input signal to turn on the first-side switching device.

19. The power converter of claim 18 , wherein the pulse generator asserts the first pulse signal at a first time when an off-time duration of the first input signal is shorter than the given time interval, the first time being a time at which the given time interval elapses after the input signal has been de-asserted.

20. The power converter of claim 18 , wherein the given time interval further includes a second time interval when the output signal is settled to have a non-negative value, the second time interval immediately following the first time interval and being equal to or shorter than 0.1%, 0.3%, 0.5%, 1%, 3%, 5%, 10%, 25%, or 50% of the first time interval.