Multi-level micro-device tethers
An exemplary wafer structure comprises a source wafer having a patterned sacrificial layer defining anchor portions separating sacrificial portions. A patterned device layer is disposed on or over the patterned sacrificial layer, forming a device anchor on each of the anchor portions. One or more devices are disposed in the patterned device layer, each device disposed entirely over a corresponding one of the one or more sacrificial portions and spatially separated from the one or more device anchors. A tether structure connects each device to a device anchor. The tether structure comprises a tether device portion disposed on or over the device, a tether anchor portion disposed on or over the device anchor, and a tether connecting the tether device portion to the tether anchor portion. The tether is disposed at least partly in the patterned device layer between the device and the device anchor.
1. A wafer structure, comprising:
a source wafer comprising a patterned sacrificial layer defining one or more anchor portions laterally separating one or more sacrificial portions;
a patterned device layer disposed at least partially on or over the patterned sacrificial layer forming a device anchor disposed on each of the one or more anchor portions;
one or more devices disposed in the patterned device layer, each of the one or more devices disposed entirely over a corresponding one of the one or more sacrificial portions and spatially separated from the one or more device anchors; and
a tether structure connecting each of the one or more devices to the device anchor disposed on one of the one or more anchor portions, the tether structure comprising a tether device portion disposed at least partly on or over the device, a tether anchor portion disposed at least partly on or over the device anchor, and a tether connecting the tether device portion to the tether anchor portion, wherein the tether structure is physically continuous and the tether is disposed at least partly in the patterned device layer between the device and the device anchor.
2. The wafer structure of claim 1 , wherein the device is spatially separated from the device anchor by a first length and the tether has a second length exclusively in a level with the device that is less than the first length.
3. The wafer structure of claim 2 , wherein the tether has a tether thickness and the second length plus twice the tether thickness has a range of 0.5 to 1.5 times the first length.
4. The wafer structure of claim 2 , wherein the wafer structure has a minimum patternable feature size and wherein the second length is less than the minimum patternable feature size.
5. The wafer structure of claim 1 , wherein the source wafer comprises one or more of a semiconductor, a compound semiconductor, GaAs, a sapphire wafer, silicon {1 0 0}, or silicon {1 1 1}.
6. The wafer structure of claim 1 , wherein the one or more devices are each a light-emitting diode or an integrated circuit.
7. The wafer structure of claim 1 , wherein the source wafer comprises a wafer material and the patterned sacrificial layer comprises a sacrificial material that is differentially etchable from the wafer material or wherein the source wafer comprises an anisotropically etchable wafer material and the patterned sacrificial layer comprises a designated portion of the anisotropically etchable material.
8. The wafer structure of claim 1 , wherein the device and the device anchor comprise a common material or wherein the device comprises a substrate material and the device anchor comprises the substrate material.
9. The wafer structure of claim 1 , wherein the device comprises a material not found in the device anchor or wherein the device comprises a substrate material and the device anchor comprises a material different from the substrate material.
10. The wafer structure of claim 1 , wherein the device is a micro-transfer printed device disposed on or over the sacrificial portion and the device comprises or is connected to a fractured or separated tether.
11. The wafer structure of claim 1 , wherein the tether substantially forms a right angle with the device anchor in a plane in the patterned device layer and substantially parallel to a surface of the source wafer on which the patterned device layer is disposed.
12. The wafer structure of claim 1 , comprising one or more device substrates, each device substrate disposed entirely over the corresponding one of the one or more sacrificial portions and under one of the one or more devices and the one of the one or more devices comprises one or more elements disposed on or over each of the device substrates.
13. The wafer structure of claim 12 , wherein the one or more elements each comprise or is connected to a fractured tether.
14. The wafer structure of claim 1 , wherein the device layer comprises GaAs, the one or more devices do not extend through the GaAs, and the one or more sacrificial portions comprises a layer of AlGaAs.
15. A wafer structure, comprising:
a source wafer comprising a patterned sacrificial layer defining one or more anchor portions separating one or more sacrificial portions;
a device layer disposed at least partially on or over the patterned sacrificial layer;
one or more devices disposed in the device layer, each of the one or more devices disposed entirely over a corresponding one of the one or more sacrificial portions and spatially separated from the one or more anchor portions; and
a tether structure connecting each of the one or more devices to one of the one or more anchor portions, the tether structure comprising a tether device portion disposed at least partly on or over the device, a tether anchor portion disposed at least partly on or over the one of the one or more anchor portions, and a tether connecting the tether device portion to the tether anchor portion,
wherein (i) the tether structure is physically continuous, (ii) the tether is disposed at least partly in a common plane with the device layer between the tether anchor portion and the tether device portion, and (iii) the tether anchor portion and the tether device portion extend above the tether.
16. The wafer structure of claim 15 , wherein the device is spatially separated from the device anchor by a first length and the tether has a second length exclusively in a level with the device that is less than the first length.
17. The wafer structure of claim 16 , wherein the tether has a tether thickness and the second length plus twice the tether thickness has a range of 0.5 to 1.5 times the first length.
18. The wafer structure of claim 16 , wherein the wafer structure has a minimum patternable feature size and wherein the second length is less than the minimum patternable feature size.
19. The wafer structure of claim 15 , wherein the source wafer comprises one or more of a semiconductor, a compound semiconductor, GaAs, a sapphire wafer, silicon {1 0 0}, or silicon {1 1 1}.
20. The wafer structure of claim 15 , wherein the one or more devices are each a light-emitting diode or an integrated circuit.
21. The wafer structure of claim 15 , wherein the source wafer comprises a wafer material and the patterned sacrificial layer comprises a sacrificial material that is differentially etchable from the wafer material or wherein the source wafer comprises an anisotropically etchable wafer material and the patterned sacrificial layer comprises a designated portion of the anisotropically etchable material.
22. The wafer structure of claim 15 , wherein the device and the device anchor comprise a common material or wherein the device comprises a substrate material and the device anchor comprises the substrate material.
23. The wafer structure of claim 15 , wherein the device comprises a material not found in the device anchor or wherein the device comprises a substrate material and the device anchor comprises a material different from the substrate material.
24. The wafer structure of claim 15 , wherein the device is a micro-transfer printed device disposed on or over the sacrificial portion and the device comprises or is connected to a fractured or separated tether.
25. The wafer structure of claim 15 , wherein the tether substantially forms a right angle with the device anchor in a plane in the patterned device layer and substantially parallel to a surface of the source wafer on which the patterned device layer is disposed.
26. The wafer structure of claim 15 , comprising one or more device substrates, each device substrate disposed entirely over the corresponding one of the one or more sacrificial portions and under one of the one or more devices and the one of the one or more devices comprises one or more elements disposed on or over each of the device substrates.
27. The wafer structure of claim 26 , wherein the one or more elements each comprise or is connected to a fractured tether.
28. The wafer structure of claim 15 , wherein the device layer comprises GaAs, the one or more devices do not extend through the GaAs, and the one or more sacrificial portions comprises a layer of AlGaAs.