Bipolar transistor semiconductor device
On a single-crystal semiconductor substrate with an upper surface including a first direction in which an inverted mesa step extends and a second direction in which a forward mesa step extends in response to anisotropic etching in which an etching rate depends on crystal plane orientation, a bipolar transistor including a collector layer, a base layer, and an emitter layer that are epitaxially grown, and a base wire connected to the base layer are arranged. A step is provided at an edge of the base layer, and the base wire is extended from inside to outside of the base layer in a direction intersecting the first direction in a plan view. An intersection of the edge of the base layer and the base wire has a disconnection prevention structure that makes it difficult for step-caused disconnection of the base wire to occur.
1. A semiconductor device comprising:
a single-crystal semiconductor substrate with an upper surface;
a first bipolar transistor including a first collector layer, a first base layer, and a first emitter layer, wherein the first collector layer, the first base layer, and the first emitter layer are epitaxially grown on the semiconductor substrate, wherein the first collector layer has a rectangular shape when the semiconductor device is viewed in a plan view, and a short-side direction of the rectangular shape is a first direction and a long-side direction of the rectangular shape is a second direction orthogonal to the first direction; and
a first base wire connected to the first base layer, wherein:
a step is provided at an edge of the first base layer, the first base wire is extended from inside to outside of the first base layer in a direction intersecting with the first direction in a plan view, and
an intersection of the edge of the first base layer and the first base wire has a disconnection prevention structure making it difficult for step-caused disconnection of the first base wire to occur, compared with a structure in which an inverted mesa step formed by anisotropic etching of the first base layer and the first collector layer intersects with the first base layer,
wherein the base wire is extended from inside to outside of the base layer as a straight line in the second direction.
2. The semiconductor device according to claim 1 , further comprising:
a sub-collector layer provided between the semiconductor substrate and the first collector layer, the sub-collector layer having a higher dopant concentration than the first collector layer, wherein:
a step with a height reaching the sub-collector layer is provided at an edge of the first collector layer,
a first collector electrode ohmic-connected to the sub-collector layer outside the first collector layer is provided,
a circuit element arranged on the first collector layer outside the first base layer and connected to the first base wire is provided, the first collector layer spreading outside the first base layer,
an inverted mesa step is formed at an edge extending in the first direction of the first collector layer, and
the step provided at the edge of the first base layer is made perpendicular to the upper surface of the semiconductor substrate or made into a forward mesa step in the first direction, thereby configuring the disconnection prevention structure.
3. The semiconductor device according to claim 2 , further comprising:
a first base electrode ohmic-connected to the first base layer, wherein:
the first base wire includes a straight-line portion extending linearly from the edge of the first base layer to the inside of the first base layer in a plan view,
the first base electrode includes a straight-line portion overlapping with the straight-line portion of the first base wire,
the straight-line portion of the first base wire is connected to the straight-line portion of the first base electrode, and
semiconductor portions each constituting the first emitter layer are arranged on both sides of the first base electrode.
4. The semiconductor device according to claim 3 , wherein:
a dimension in a height direction of the step provided at the edge of the first base layer is smaller than a dimension in a thickness direction of the first base wire.
5. The semiconductor device according to claim 3 , further comprising:
a second bipolar transistor including a second collector layer, a second base layer, and a second emitter layer, wherein the second collector layer, the second base layer, and the second emitter layer are epitaxially grown on the semiconductor substrate; and
a second base wire connected to the second base layer, wherein:
a step is provided at an edge of the second base layer, and
the second base wire is extended from inside to outside of the second base layer so as to intersect with an edge extending in the second direction of the second base layer in a plan view.
6. The semiconductor device according to claim 2 , wherein:
a dimension in a height direction of the step provided at the edge of the first base layer is smaller than a dimension in a thickness direction of the first base wire.
7. The semiconductor device according to claim 2 , further comprising:
a second bipolar transistor including a second collector layer, a second base layer, and a second emitter layer, wherein the second collector layer, the second base layer, and the second emitter layer are epitaxially grown on the semiconductor substrate; and
a second base wire connected to the second base layer, wherein:
a step is provided at an edge of the second base layer, and the second base wire is extended from inside to outside of the second base layer so as to intersect with an edge extending in the second direction of the second base layer in a plan view.
8. The semiconductor device according to claim 1 , wherein:
a dimension in a height direction of the step provided at the edge of the first base layer is smaller than a dimension in a thickness direction of the first base wire.
9. The semiconductor device according to claim 8 , further comprising:
a second bipolar transistor including a second collector layer, a second base layer, and a second emitter layer, wherein the second collector layer, the second base layer, and the second emitter layer are epitaxially grown on the semiconductor substrate; and
a second base wire connected to the second base layer, wherein:
a step is provided at an edge of the second base layer, and the second base wire is extended from inside to outside of the second base layer so as to intersect with an edge extending in the second direction of the second base layer in a plan view.
10. The semiconductor device according to claim 1 , wherein:
the step provided at the edge of the first base layer has a height reaching a bottom surface of the first collector layer,
the edge of the first base layer extends in the first direction from the intersection of the edge of the first base layer and the first base wire,
the edge of the first base layer extends in a direction shifted from the first direction at a place where the edge of the first base layer and the first base wire overlap with each other, and
the step provided at the edge of the first base layer is an inverted mesa step on both sides of the first base wire, and is perpendicular or is a forward mesa step at a position overlapping the first base wire, thereby configuring the disconnection prevention structure.
11. The semiconductor device according to claim 10 , further comprising:
a first base electrode arranged on the first base layer and having a linear shape extending in the second direction, wherein:
semiconductor portions each constituting the first emitter layer are arranged on both sides of the first base electrode,
the first base electrode extends to outside an area where the first emitter layers are arranged regarding the second direction, and includes a widened portion being wider in an inverted tapered shape as the widened portion extends farther away from the first emitter layers in the second direction, and
the first base wire is connected to the widened portion of the first base electrode.
12. The semiconductor device according to claim 11 , further comprising:
a second bipolar transistor including a second collector layer, a second base layer, and a second emitter layer, wherein the second collector layer, the second base layer, and the second emitter layer are epitaxially grown on the semiconductor substrate; and
a second base wire connected to the second base layer, wherein:
a step is provided at an edge of the second base layer, and
the second base wire is extended from inside to outside of the second base layer so as to intersect with an edge extending in the second direction of the second base layer in a plan view.
13. The semiconductor device according to claim 10 , further comprising:
a second bipolar transistor including a second collector layer, a second base layer, and a second emitter layer, wherein the second collector layer, the second base layer, and the second emitter layer are epitaxially grown on the semiconductor substrate; and
a second base wire connected to the second base layer, wherein:
a step is provided at an edge of the second base layer, and
the second base wire is extended from inside to outside of the second base layer so as to intersect with an edge extending in the second direction of the second base layer in a plan view.
14. The semiconductor device according to claim 1 , further comprising:
a second bipolar transistor including a second collector layer, a second base layer, and a second emitter layer, wherein the second collector layer, the second base layer, and the second emitter layer are epitaxially grown on the semiconductor substrate; and
a second base wire connected to the second base layer, wherein:
a step is provided at an edge of the second base layer, and
the second base wire is extended from inside to outside of the second base layer so as to intersect with an edge extending in the second direction of the second base layer in a plan view.