Magnetic memory
Provided is a magnetic memory including: a first bit line, a second bit line, and a third bit line; a word line; a first magnetoresistance effect element; a first transistor; a second magnetoresistance effect element; and a second transistor, wherein free layers of the first and second magnetoresistance effect elements and the second bit line are connected, a fixed layer of the first magnetoresistance effect element and a source terminal of the first transistor are connected, a drain terminal of the first transistor and the first bit line are connected, a fixed layer of the second magnetoresistance effect element and a drain terminal of the second transistor are connected, a source terminal of the second transistor and the third bit line are connected, and the word line is connected to each of a gate terminal of the first transistor and a gate terminal of the second transistor.
1. A magnetic memory comprising:
a first bit line, a second bit line, and a third bit line;
a word line;
a first magnetoresistance effect element;
a first transistor;
a second magnetoresistance effect element; and
a second transistor, wherein
a series circuit of the first magnetoresistance effect element and the first transistor is present between the first bit line and the second bit line,
a free layer of the first magnetoresistance effect element and the second bit line are connected to each other,
a fixed layer of the first magnetoresistance effect element and a source terminal of the first transistor are connected to each other,
a drain terminal of the first transistor and the first bit line are connected to each other,
a series circuit of the second magnetoresistance effect element and the second transistor is present between the second bit line and the third bit line,
a free layer of the second magnetoresistance effect element and the second bit line are connected to each other,
a fixed layer of the second magnetoresistance effect element and a drain terminal of the second transistor are connected to each other,
a source terminal of the second transistor and the third bit line are connected to each other, and
the word line is connected to each of a gate terminal of the first transistor and a gate terminal of the second transistor.
2. The magnetic memory according to claim 1 , wherein the magnetic memory is configured for a spin orbit torque to be induced by applying a voltage difference between both ends of the second bit line.
3. The magnetic memory according to claim 2 , further comprising:
a first switching circuit, a second switching circuit, a third switching circuit, and a fourth switching circuit;
a first voltage generating circuit, a second voltage generating circuit, a third voltage generating circuit, and a fourth voltage generating circuit; and
a row decoder, wherein
one end of the first switching circuit is connected to one end of the first bit line, and the other end of the first switching circuit is connected to the first voltage generating circuit,
one end of the second switching circuit is connected to one end of the second bit line, and the other end of the second switching circuit is connected to the second voltage generating circuit,
one end of the third switching circuit is connected to the other end of the second bit line, and the other end of the third switching circuit is connected to the third voltage generating circuit,
one end of the fourth switching circuit is connected to one end of the third bit line, and the other end of the fourth switching circuit is connected to the fourth voltage generating circuit, and
the row decoder is connected to one end of the word line.
4. The magnetic memory according to claim 2 , wherein
each of the free layer of the first magnetoresistance effect element and the free layer of the second magnetoresistance effect element is conductively connected to a first face and a second face of the second bit line facing each other, respectively.
5. The magnetic memory according to claim 4 , wherein
at least a part of a face, on which the free layer of the first magnetoresistance effect element contacts the first face of the second bit line, and a face, on which the free layer of the second magnetoresistance effect element contacts the second face of the second bit line, overlaps at a first connection point at which the free layer of the first magnetoresistance effect element is conductively connected to the first face of the second bit line and a second connection point at which the free layer of the second magnetoresistance effect element is conductively connected to the second face of the second bit line, as viewed in a direction perpendicular to the first face and the second face.
6. The magnetic memory according to claim 5 , further comprising:
a first switching circuit, a second switching circuit, a third switching circuit, and a fourth switching circuit;
a first voltage generating circuit, a second voltage generating circuit, a third voltage generating circuit, and a fourth voltage generating circuit; and
a row decoder, wherein
one end of the first switching circuit is connected to one end of the first bit line, and the other end of the first switching circuit is connected to the first voltage generating circuit,
one end of the second switching circuit is connected to one end of the second bit line, and the other end of the second switching circuit is connected to the second voltage generating circuit,
one end of the third switching circuit is connected to the other end of the second bit line, and the other end of the third switching circuit is connected to the third voltage generating circuit,
one end of the fourth switching circuit is connected to one end of the third bit line, and the other end of the fourth switching circuit is connected to the fourth voltage generating circuit, and
the row decoder is connected to one end of the word line.
7. The magnetic memory according to claim 4 , further comprising:
a first switching circuit, a second switching circuit, a third switching circuit, and a fourth switching circuit;
a first voltage generating circuit, a second voltage generating circuit, a third voltage generating circuit, and a fourth voltage generating circuit; and
a row decoder, wherein
one end of the first switching circuit is connected to one end of the first bit line, and the other end of the first switching circuit is connected to the first voltage generating circuit,
one end of the second switching circuit is connected to one end of the second bit line, and the other end of the second switching circuit is connected to the second voltage generating circuit,
one end of the third switching circuit is connected to the other end of the second bit line, and the other end of the third switching circuit is connected to the third voltage generating circuit,
one end of the fourth switching circuit is connected to one end of the third bit line, and the other end of the fourth switching circuit is connected to the fourth voltage generating circuit, and
the row decoder is connected to one end of the word line.
8. The magnetic memory according to claim 1 , wherein
each of the free layer of the first magnetoresistance effect element and the free layer of the second magnetoresistance effect element is conductively connected to a first face and a second face of the second bit line facing each other, respectively.
9. The magnetic memory according to claim 8 , wherein
at least a part of a face, on which the free layer of the first magnetoresistance effect element contacts the first face of the second bit line, and a face, on which the free layer of the second magnetoresistance effect element contacts the second face of the second bit line, overlaps at a first connection point at which the free layer of the first magnetoresistance effect element is conductively connected to the first face of the second bit line and a second connection point at which the free layer of the second magnetoresistance effect element is conductively connected to the second face of the second bit line, as viewed in a direction perpendicular to the first face and the second face.
10. The magnetic memory according to claim 9 , further comprising:
a first switching circuit, a second switching circuit, a third switching circuit, and a fourth switching circuit;
a first voltage generating circuit, a second voltage generating circuit, a third voltage generating circuit, and a fourth voltage generating circuit; and
a row decoder, wherein
one end of the first switching circuit is connected to one end of the first bit line, and the other end of the first switching circuit is connected to the first voltage generating circuit,
one end of the second switching circuit is connected to one end of the second bit line, and the other end of the second switching circuit is connected to the second voltage generating circuit,
one end of the third switching circuit is connected to the other end of the second bit line, and the other end of the third switching circuit is connected to the third voltage generating circuit,
one end of the fourth switching circuit is connected to one end of the third bit line, and the other end of the fourth switching circuit is connected to the fourth voltage generating circuit, and
the row decoder is connected to one end of the word line.
11. The magnetic memory according to claim 8 , further comprising:
a first switching circuit, a second switching circuit, a third switching circuit, and a fourth switching circuit;
a first voltage generating circuit, a second voltage generating circuit, a third voltage generating circuit, and a fourth voltage generating circuit; and
a row decoder, wherein
one end of the first switching circuit is connected to one end of the first bit line, and the other end of the first switching circuit is connected to the first voltage generating circuit,
one end of the second switching circuit is connected to one end of the second bit line, and the other end of the second switching circuit is connected to the second voltage generating circuit,
one end of the third switching circuit is connected to the other end of the second bit line, and the other end of the third switching circuit is connected to the third voltage generating circuit,
one end of the fourth switching circuit is connected to one end of the third bit line, and the other end of the fourth switching circuit is connected to the fourth voltage generating circuit, and
the row decoder is connected to one end of the word line.
12. The magnetic memory according to claim 1 , further comprising:
a first switching circuit, a second switching circuit, a third switching circuit, and a fourth switching circuit;
a first voltage generating circuit, a second voltage generating circuit, a third voltage generating circuit, and a fourth voltage generating circuit; and
a row decoder, wherein
one end of the first switching circuit is connected to one end of the first bit line, and the other end of the first switching circuit is connected to the first voltage generating circuit,
one end of the second switching circuit is connected to one end of the second bit line, and the other end of the second switching circuit is connected to the second voltage generating circuit,
one end of the third switching circuit is connected to the other end of the second bit line, and the other end of the third switching circuit is connected to the third voltage generating circuit,
one end of the fourth switching circuit is connected to one end of the third bit line, and the other end of the fourth switching circuit is connected to the fourth voltage generating circuit, and
the row decoder is connected to one end of the word line.
13. The magnetic memory according to claim 12 , wherein
the magnetic memory is configured in such way that an identical data are written on the first magnetoresistance effect element and the second magnetoresistance effect element by: an SOT current flowing to the second bit line due to application of an electric potential difference between the second voltage generating circuit and the third voltage generating circuit; and an STT current flowing to both of the first magnetoresistance effect element and the second magnetoresistance effect element due to application of an electric potential difference between the first voltage generating circuit and the fourth voltage generating circuit at a timing after start of flowing of the SOT current for a predetermined voltage to be applied to the word line.
14. The magnetic memory according to claim 12 , wherein
the magnetic memory is configured in such way that data are written on one of the first magnetoresistance effect element and the second magnetoresistance effect element by: an SOT current flowing to the second bit line due to application of an electric potential difference between the second voltage generating circuit and the third voltage generating circuit; and an STT current flowing to the one of the first magnetoresistance effect element and the second magnetoresistance effect element due to application of an electric potential difference between the first voltage generating circuit and the fourth voltage generating circuit at a timing after start of flowing of the SOT current for a predetermined voltage to be applied to the word line.