Clock generating circuitry

1. An integrated circuit, comprising:

a first pulse generator that generates a first clock pulse for a two pulse sequence based on one or more input signals; and

a second pulse generator that is coupled to the first pulse generator and that generates a second clock pulse for the two pulse sequence based on the one or more input signals, wherein the second pulse generator has a single stack clock driver that provides an output clock signal having the two pulse sequence.

2. The integrated circuit of claim 1 , wherein the two pulse sequence comprises a negative global timing pulse (NGTP) for double-pumped memory applications.

3. The integrated circuit of claim 1 , wherein the single stack clock driver comprises a single transistor that operates as the single stack clock driver, and wherein the single stack clock driver is used to save area and clock power by reducing per cycle clock switching power.

4. The integrated circuit of claim 3 , wherein the single transistor comprises an N-type metal-oxide semiconductor (NMOS) transistor.

5. The integrated circuit of claim 1 , further comprising an input circuit having multiple logic gates arranged in sequence to receive the one or more input signals and provide an activation signal to the single stack clock driver.

6. The integrated circuit of claim 5 , wherein the multiple logic gates of the input circuit include a NAND gate and multiple NOR gates.

7. The integrated circuit of claim 5 , further comprising a first feedback circuit having multiple logic gates arranged in sequence to receive the activation signal and the output clock signal and provide a first feedback signal as the one or more input signals.

8. The integrated circuit of claim 7 , wherein the multiple logic gates of the first feedback circuit include an AND-OR-Invert (AOI) single inversion gate and multiple inverters.

9. The integrated circuit of claim 7 , further comprising a second feedback circuit having multiple logic gates arranged in sequence to receive at least one input signal of the one or more input signals and provide a second feedback signal to at least one logic gate of the multiple logic gates of the first feedback circuit.

10. The integrated circuit of claim 9 , wherein the single stack clock driver is driven by a logic gate to thereby provide tolerance to variation since an input load on a clock input pin is reduced significantly, and wherein the logic gate is implemented with an AND gate.

11. An integrated circuit, comprising:

a pulse generating circuit that generates a pulse for a global timing sequence based on at least one input clock signal,

wherein the pulse generating circuit has a single stack clock driving circuit that provides a negative global timing pulse (NGTP) signal with the pulse as at least one clock pulse per cycle for the global timing sequence.

12. The integrated circuit of claim 11 , wherein the global timing sequence comprises a two pulse global timing sequence, and further comprising:

an additional pulse generating circuit that generates another pulse prior to the pulse for the two pulse global timing sequence based on multiple input clock signals,

wherein the additional pulse generating circuit is coupled to the pulse generating circuit that generates the pulse for the two pulse global timing sequence based on the multiple input clock signals, and

wherein the single stack clock driving circuit and the additional pulse generating circuit provide the NGTP signal having the two pulse global timing sequence with the prior pulse and the pulse.

13. The integrated circuit of claim 12 , wherein the single stack clock driving circuit comprises a single transistor that operates as the single stack clock driver, and wherein the single stack clock driver is used to save area and clock power by reducing per cycle clock switching power.

14. The integrated circuit of claim 12 further comprising an input circuit having multiple logic gates arranged in sequence to receive the multiple input signals and provide an activation signal to the single stack clock driving circuit.

15. The integrated circuit of claim 14 , wherein the multiple logic gates of the input circuit include a NAND gate and multiple NOR gates.

16. The integrated circuit of claim 14 , further comprising a first feedback circuit having multiple logic gates arranged in sequence to receive the activation signal and the negative global timing pulse (NGTP) signal and provide a first feedback signal to the input circuit as one of the multiple input clock signals.

17. The integrated circuit of claim 16 , wherein the multiple logic gates of the first feedback circuit includes an AND-OR-Invert (AOI) single inversion gate and multiple inverters.

18. The integrated circuit of claim 16 , further comprising a second feedback circuit having multiple logic gates arranged in sequence to receive at least one input signal of the multiple input signals and provide a second feedback signal to at least one logic gate of the multiple logic gates of the first feedback circuit.

19. The integrated circuit of claim 18 , wherein the single stack clock driving circuit is driven by a logic gate to thereby provide tolerance to variation since an input load on a clock input pin is reduced significantly, and wherein the logic gate is implemented with an AND gate.

20. A method for manufacturing an integrated circuit, comprising:

fabricating a first pulse generator that generates a first clock pulse for a two pulse sequence based on one or more input signals; and

fabricating a second pulse generator that is coupled to the first pulse generator and that generates a second clock pulse for the two pulse sequence based on the one or more input signals, wherein the second pulse generator has a single stack clock driver that provides an output clock signal having the two pulse sequence.