Methods of Manufacturing Three-Dimensional Arrays with Magnetic Tunnel Junction Devices Including an Annular Free Magnetic Layer and a Planar Reference Magnetic Layer

1 . A method of manufacturing a Magnetic Tunnel Junction (MTJ) comprising;

forming a first planar non-magnetic insulator layer;

forming a planar reference magnetic layer on the first planar non-magnetic insulator layer;

forming a second planar non-magnetic insulator layer on the planar reference magnetic layer;

forming one or more annular openings through the second planar non-magnetic insulator layer, the planar reference magnetic layer and the first planar non-magnetic insulator layer;

forming an annular tunnel insulator on the walk of the one or more annular openings;

forming an annular free magnetic layer on the annular insulator inside the one or more annular openings;

forming an annular non-magnetic layer on the annular free magnetic layer inside the one or more annular openings; and

forming an annular conductive core inside the annular non-magnetic layer in the one or more annular openings.

2 . The method according to claim 1 , wherein forming the one or more annular openings comprises milling a conical opening through the second planar non-magnetic insulator layer, the planar reference magnetic layer and the first planar non-magnetic insulator layer.

3 . The method according to claim 1 , wherein the one or more annular openings have a taper of approximate 10-45 degrees from a first side of the planar reference magnetic layer to a second side of the planar reference magnetic layer.

4 . The method according to claim 1 , wherein:

a magnetic field of the planar reference magnetic layer has a fixed polarization substantially perpendicular to a major planar orientation of the planar reference magnetic layer; and

a magnetic field of the annular free magnetic layer has a polarization substantially perpendicular to the major planar orientation of the planar reference magnetic layer and selectively switchable between being substantially parallel and substantially antiparallel to the magnetic field of the planar reference layer.

5 . The method according to claim 1 , wherein forming the annular tunnel insulator, the annular free magnetic layer and the annular non-magnetic layer comprises:

depositing a tunnel insulator layer on the surface of the second planar non-magnetic insulator layer and inside the one or more annular openings;

depositing a free magnetic layer on the surface of the annular tunnel insulator inside and outside the one or more annular openings;

depositing a non-magnetic layer on the surface of the annular free magnetic layer on the surface of the annular free magnetic layer inside and outside the one or more annular openings; and

selectively etching portions of the annular tunnel insulator, the annular free magnetic layer and the annular non-magnetic layer from the surface of the second planar non-magnetic insulator layer outside the one or more annular openings and at a bottom of the one or more annular openings.

6 . The method according to claim 1 , wherein the annular tunnel insulator, the annular free magnetic layer and the annular non-magnetic layer are deposited using a directional deposition process.

7 . The method according to claim 1 , wherein forming the annular conductive core comprises:

depositing a conductor layer on the surface of the second planar non-magnetic insulator layer and inside the annular non-magnetic layer in the one or more annular openings; and

Chemical Mechanical Polishing (CMP) the conductor layer to remove the portion of the conductor layer from the surface of the second planar non-magnetic insulator layer outside the one or more annular openings.

8 . A method of manufacturing a memory cell array comprising:

forming a first planar non-magnetic insulator layer on a plurality of selectors;

forming a first planar reference magnetic layer on the first planar non-magnetic insulator layer;

forming a second planar non-magnetic insulator layer on the first planar reference magnetic layer;

forming a first array of annular openings through the second planar non-magnetic insulator layer, the first planar reference magnetic layer and the first planar non-magnetic insulator layer;

forming an annular tunnel insulator on the walls of the first array of annular openings;

forming an annular free magnetic layer on the annular insulator inside the first array of annular openings;

forming an annular non-magnetic layer on the annular free magnetic layer inside the first array of annular openings; and

forming an annular conductive core inside the annular non-magnetic layer in the first array of annular openings.

9 . The method of manufacturing a memory cell array according to claim 8 , further comprising;

selectively removing a portion of the second planar non-magnetic insulator layer in a periphery region to expose the planar reference magnetic layer;

forming a bit line on the portion of the exposed planar reference magnetic layer.

10 . The method of manufacturing a memory cell array according to claim 8 , further comprising:

forming a third planar non-magnetic insulator layer on the second planar non-magnetic insulator layer;

forming a second planar reference magnetic layer on the third planar non-magnetic insulator layer;

forming a fourth planar non-magnetic insulator layer on the second planar reference magnetic layer;

forming a second array of annular openings through the fourth planar non-magnetic insulator layer, the second planar reference magnetic layer and the third planar non-magnetic insulator layer, wherein the second array of annular opening are aligned with the first array of annular openings;

forming an annular tunnel insulator on the walls of the second array of annular openings;

forming an annular free magnetic layer on the annular insulator inside the second array of annular openings;

forming an annular non-magnetic layer on the annular free magnetic layer inside the second array of annular openings; and

forming an annular conductive core inside the annular non-magnetic layer in the second array of annular openings.

11 . The method of manufacturing a memory cell array according to 10 , further comprising:

selectively removing a portion of the fourth planar non-magnetic insulator layer, the second planar reference magnetic layer, the third planar non-magnetic layer and the second planar non-magnetic insulator layer in a periphery region to expose the first and second planar reference magnetic layers;

forming a first bit line on the portion of the exposed first planar reference magnetic layer and a second bit line on the portion of the exposed second planar reference magnetic layer.

12 . The method of manufacturing a memory cell array according to 11 , further comprising:

forming a first global bit line coupled to the first bit line and one or more additional bit lines in a first row; and

forming a second global bit line coupled to the second bit line and one or more additional bit lines in a second row.

13 . The method of manufacturing the, memory cell array according to claim 8 , wherein the first array of annular openings are formed with a sidewall taper of approximately 10-45 degrees from a first side of the planar reference magnetic layer to a second side of the planar reference magnetic layer.

14 . The method a manufacturing the memory cell array according to claim 13 , wherein the annular tunnel insulator, the annular free magnetic layer, and the annular non-magnetic layer are deposited on the sidewalls of the first array of annular openings using a directional deposition process.

15 . The method of manufacturing the memory cell array according to claim 8 , wherein:

a magnetic field of the planar reference magnetic layer has a fixed polarization substantially perpendicular to a major planar orientation of the planar reference magnetic layer; and

a magnetic field of the annular free magnetic layer has a polarization substantially perpendicular to the major planar orientation of the planar reference magnetic layer and selectively switchable between being substantially parallel and substantially antiparallel to the magnetic field of the planar reference layer.

16 . A method of manufacturing a memory cell array comprising:

forming a first planar non-magnetic insulator layer on a plurality of selectors;

forming a first planar reference magnetic layer on the first planar non-magnetic insulator layer;

forming a second planar non-magnetic insulator layer on the first planar reference magnetic layer;

forming a third planar non-magnetic insulator layer on the second planar non-magnetic insulator layer;

forming a second planar reference magnetic layer on the third planar non-magnetic insulator layer;

forming a fourth planar non-magnetic insulator layer on the second planar reference magnetic layer;

forming an array of annular openings through the fourth planar non-magnetic insulator layer, the second planar reference magnetic layer, the third and second planar non-magnetic insulator layers, the first planar reference magnetic layer and the first planar non-magnetic insulator layer;

forming an annular tunnel insulator on the walls of the array of annular openings;

forming an annular free magnetic layer on the annular insulator inside the array of annular openings;

forming non-magnetic regions in the annular free magnetic layer to separate the annular free magnetic layer into a plurality of portions aligned with the first and second planar reference magnetic layers;

forming an annular non-magnetic layer on the annular free magnetic layer inside the array of annular openings; and

forming an annular conductive core inside the annular non-magnetic layer in the array of annular openings.

17 . The method of manufacturing a memory cell array according to 16 , further comprising:

selectively removing a portion of the fourth planar non-magnetic insulator layer, the second planar reference magnetic layer, the third planar non-magnetic layer and the second planar non-magnetic insulator layer in, a periphery region to expose the first and second planar reference magnetic layers;

forming a first bit line on the portion of the exposed first planar reference magnetic layer and a second bit line on the portion of the exposed second planar reference magnetic layer.

18 . The method of manufacturing a memory cell array according to 17 , further comprising:

forming a first global bit line coupled to the first bit line and one or more additional bit lines in a first row; and

forming a second global bit line coupled to the second bit line and one or more additional bit lines in a second row.

19 . The method of manufacturing, the memory cell array according to claim 16 , wherein the array of annular openings are formed with a sidewall taper of approximately 10-45 degrees.

20 . The method of manufacturing the memory cell array according to claim 21 , wherein the annular tunnel insulator, the annular free magnetic layer and the annular non-magnetic layer are deposited on the sidewalls of the array of annular openings using a directional deposition process.

21 . The method of manufacturing the memory cell array according to claim 16 , wherein:

a magnetic field of the first and second planar reference magnetic layers have a fixed polarization substantially perpendicular to a major planar orientation of the first and second planar reference magnetic layers; and

a magnetic field of the annular free magnetic layer has a polarization substantially perpendicular to the major planar orientation of the first and second planar reference magnetic layers and selectively switchable between being substantially parallel and substantially antiparallel to the magnetic field of the first and second planar reference layers.

22 . The method of manufacturing the memory cell array according to claim 16 , wherein forming the non-magnetic regions in the annular free magnetic layer comprises:

forming a metal diffusion layer between the second and third planar non-magnetic insulator layers, wherein metal from the metal diffusion layer diffuses into the annular free magnetic layer to form the non-magnetic regions in the annular free magnetic layer.

23 . The method of manufacturing the memory cell array according to claim 16 , wherein forming the non-magnetic regions in the annular free magnetic layer comprises:

implanting a metal into a region in the annular free magnetic layer between the second and third planar non-magnetic insulator layers to form the non-magnetic regions in the annular free magnetic layer.