Patent Assignment
Reel/Frame 049421/0501
Change of Name
Recorded: 2019-06-10
Pages: 32
Assignor
SPIN TRANSFER TECHNOLOGIES, INC.
Executed: 2018-11-08
Assignee
SPIN MEMORY, INC.
45500 NORTHPORT LOOP WEST, FREMONT, CALIFORNIA, 94538
Covered Properties
(64)
Spin Transfer Torque Mram Device with Error Buffer
Patent:
10,115,446 →
Application:
15/132,544 →
Method and Apparatus for Bipolar Memory Write-Verify
Device with Dynamic Redundancy Registers
Method and Apparatus for Bipolar Memory Write-Verify
On-The-Fly Bit Failure Detection and Bit Redundancy Remapping Techniques to Correct for Fixed Bit Defects
Method of Reading Data from a Memory Device Using Multiple Levels of Dynamic Redundancy Registers
A Memory Device Using Levels of Dynamic Redundancy Registers for Writing a Data Word That Failed a Write Operation
A Method of Processing Incomplete Memory Operations in a Memory Device During a Power Up Sequence and a Power Down Sequence Using a Dynamic Redundancy Register
Method of Flushing the Contents of a Dynamic Redundancy Register to a Secure Storage Area During a Power Down in a Memory Device
Method of Writing Contents in Memory During a Power Up Sequence Using a Dynamic Redundancy Register in a Memory Device
Shared Bit Line Array Architecture for Magnetoresistive Memory
Memory Instruction Pipeline with a Pre-Read Stage for a Write Operation for Reducing Power Consumption in a Memory Device That Uses Dynamic Redundancy Registers
Magnetic Field Transducer Mounting Apparatus for MTJ Device Testers
Magnet Mounting Apparatus for MTJ Device Testers
Memory Instruction Pipeline with an Additional Write Stage in a Memory Device That Uses Dynamic Redundancy Registers
Smart Cache Design to Prevent Overflow for a Memory Device with a Dynamic Redundancy Register
Forcing Bits as Bad to Widen the Window Between the Distributions of Acceptable High and Low Resistive Bits Thereby Lowering the Margin and Increasing the Speed of the Sense Amplifiers
Forcing Stuck Bits, Waterfall Bits, Shunt Bits and Low Tmr Bits to Short During Testing and Using on-the-Fly Bit Failure Detection and Bit Redundancy Remapping Techniques to Correct Them
Memory Device with a Plurality of Memory Banks Where Each Memory Bank Is Associated with a Corresponding Memory Instruction Pipeline and a Dynamic Redundancy Register
Over-Voltage Write Operation of Tunnel Magnet-Resistance ("Tmr") Memory Device and Correcting Failure Bits Therefrom by Using on-the-Fly Bit Failure Detection and Bit Redundancy Remapping Techniques
Memory Device with a Dual Y-Multiplexer Structure for Performing Two Simultaneous Operations on the Same Row of a Memory Bank
Perpendicular Source and Bit Lines for an Mram Array
Memory Array with Horizontal Source Line and a Virtual Source Line
Memory Array with Horizontal Source Line and Sacrificial Bitline Per Virtual Source
Memory Array with Individually Trimmable Sense Amplifiers
Process for Improving Photoresist Pillar Adhesion During Mram Fabrication
Process for Hard Mask Development for Mram Pillar Formation Using Photolithography
Process for Creating Dense Pillars Using Multiple Exposures for Mram Fabrication
Photolithographic Method for Fabricating Dense Pillar Arrays Using Spacers as a Pattern
Application:
15/857,499 →
Publication:
US 2019/0207101
Multi-Port Random Access Memory
Magnetic Tunnel Junction (Mtj) Fabrication Methods and Systems
Memory Device having Overlapping Magnetic Tunnel Junctions in Compliance with a Reference Pitch
Perpendicular Magnetic Anisotropy Interface Tunnel Junction Devices and Methods of Manufacture
Methods of Manufacturing Magnetic Tunnel Junction Devices
Precessional Spin Current Magnetic Tunnel Junction Devices and Methods of Manufacture
Magnetic Tunnel Junction Devices Including an Optimization Layer
Methods of Fabricating Magnetic Tunnel Junctions Integrated with Selectors
Devices Including Magnetic Tunnel Junctions Integrated with Selectors
Magnetic Tunnel Junction Wafer Adaptor Used in Magnetic Annealing Furnace and Method of Using the Same
Magnetic Tunnel Junction Wafer Adaptor Used in Magnetic Annealing Furnace and Method of Using the Same
Process for Creating a High Density Magnetic Tunnel Junction Array Test Platform
Patent:
10,411,185 →
Application:
15/992,815 →
Multi-Bit Cell Read-Out Techniques
Read-Out Techniques for Multi-Bit Cells
Magnetic Tunnel Junction Devices Including an Annular Free Magnetic Layer and a Planar Reference Magnetic Layer
Application:
16/059,004 →
Publication:
US 2019/0296220
Three-Dimensional Arrays with Magnetic Tunnel Junction Devices Including an Annular Free Magnetic Layer and a Planar Reference Magnetic Layer
Application:
16/059,009 →
Publication:
US 2019/0296228
Three-Dimensional Arrays with Magnetic Tunnel Junction Devices Including an Annular Discontinued Free Magnetic Layer and a Planar Reference Magnetic Layer
Bit Line Structures for Three-Dimensional Arrays with Magnetic Tunnel Junction Devices Including an Annular Free Magnetic Layer and a Planar Reference Magnetic Layer
Methods of Manufacturing Three-Dimensional Arrays with Magnetic Tunnel Junction Devices Including an Annular Free Magnetic Layer and a Planar Reference Magnetic Layer
Application:
16/059,018 →
Publication:
US 2019/0296223
System for a Wide Temperature Range Nonvolatile Memory
Method of Optimizing Write Voltage Based on Error Buffer Occupancy
Magnetic Tunnel Junction Devices Including a Free Magnetic Trench Layer and a Planar Reference Magnetic Layer
Three-Dimensional Arrays with MTJ Devices Including a Free Magnetic Trench Layer and a Planar Reference Magnetic Layer
Methods of Manufacturing Three-Dimensional Arrays with MTJ Devices Including a Free Magnetic Trench Layer and a Planar Reference Magnetic Layer
Magnetic Tunnel Junction Devices Including an Annular Free Magnetic Layer and a Planar Reference Magnetic Layer
Application:
16/122,729 →
Publication:
US 2019/0295618
Multi-Bit Cell Read-Out Techniques for Mram Cells with Mixed Pinned Magnetization Orientations
Multi-Bit Cell Read-Out Techniques for Mram Cells with Mixed Pinned Magnetization Orientations
Word Line Decoder Memory Architecture
Multi Terminal Device Stack Systems and Methods
Multi Terminal Device Stack Formation Methods
Patterned Silicide Structures and Methods of Manufacture
Multi-Chip Module for Mram Devices with Levels of Dynamic Redundancy Registers.
Master Slave Level Shift Latch for Word Line Decoder Memory Architecture
Perpendicular Magnetic Anisotropy Interface Tunnel Junction Devices
Application:
16/297,553 →
Publication:
US 2019/0237664
Process for Creating a High Density Magnetic Tunnel Junction Array Test Platform
Related Assignments
(20)
Other recorded transfers of the patents in this record — the chain of ownership.
Assignment of Assignor's Interest
Apr 19, 2016
From: LOUIE, BENJAMIN STANLEY; BERGER, NEAL
To: SPIN TRANSFER TECHNOLOGIES, INC.
Reel/Frame 038318/0318 →
Assignment of Assignor's Interest
Jun 6, 2016
From: BERGER, NEAL; LOUIE, BEN; EL-BARAJI, MOURAD
To: SPIN TRANSFER TECHNOLOGIES, INC.
Reel/Frame 038820/0643 →
Assignment of Assignor's Interest
Sep 27, 2016
From: EL BARAJI, MOURAD; BERGER, NEAL; LOUIE, BENJAMIN STANLEY; CRUDELE, LESTER M.
To: SPIN TRANSFER TECHNOLOGIES, INC.
Reel/Frame 039870/0697 →
Security Interest
Jun 16, 2017
From: SPIN TRANSFER TECHNOLOGIES, INC.
To: SILICON VALLEY BANK
Reel/Frame 042981/0819 →
Assignment of Assignor's Interest
Nov 25, 2017
From: HOBERMAN, BARRY
To: SPIN TRANSFER TECHNOLOGIES, INC.
Reel/Frame 044219/0987 →
Assignment of Assignor's Interest
Dec 27, 2017
From: BERGER, NEAL; LOUIE, BENJAMIN; EL-BARAJI, MOURAD; CRUDELE, LESTER
To: SPIN TRANSFER TECHNOLOGIES, INC.
Reel/Frame 044493/0484 →
Assignment of Assignor's Interest
Dec 27, 2017
From: YAM, DANNY; VASQUEZ, JORGE; WOLF, GEORG; CORDERO, ROBERTO
To: SPIN TRANSFER TECHNOLOGIES, INC.
Reel/Frame 044493/0618 →
Assignment of Assignor's Interest
Dec 27, 2017
From: BERGER, NEAL; LOUIE, BENJAMIN; EL-BARAJI, MOURAD; CRUDELE, LESTER
To: SPIN TRANSFER TECHNOLOGIES, INC.
Reel/Frame 044493/0929 →
Assignment of Assignor's Interest
Dec 27, 2017
From: BERGER, NEAL; LOUIE, BENJAMIN; EL BARAJI, MOURAD; CRUDELE, LESTER
To: SPIN TRANSFER TECHNOLOGIES, INC.
Reel/Frame 044493/0941 →
Assignment of Assignor's Interest
Dec 27, 2017
From: BERGER, NEAL; LOUIE, BENJAMIN; EL-BARAJI, MOURAD; CRUDELE, LESTER
To: SPIN TRANSFER TECHNOLOGIES, INC.
Reel/Frame 044493/0775 →
Assignment of Assignor's Interest
Dec 27, 2017
From: BERGER, NEAL; LOUIE, BENJAMIN; EL-BARAJI, MOURAD; HILLMAN, DANIEL
To: SPIN TRANSFER TECHNOLOGIES, INC.
Reel/Frame 044491/0934 →
Assignment of Assignor's Interest
Dec 27, 2017
From: BERGER, NEAL; LOUIE, BENJAMIN; EL-BARAJI, MOURAD; CRUDELE, LESTER
To: SPIN TRANSFER TECHNOLOGIES, INC.
Reel/Frame 044492/0455 →
Assignment of Assignor's Interest
Dec 27, 2017
From: BERGER, NEAL; LOUIE, BENJAMIN; EL-BARAJI, MOURAD; CRUDELE, LESTER
To: SPIN TRANSFER TECHNOLOGIES, INC.
Reel/Frame 044493/0175 →
Assignment of Assignor's Interest
Dec 27, 2017
From: LEVI, AMITAY
To: SPIN TRANSFER TECHNOLOGIES, INC.
Reel/Frame 044493/0383 →
Assignment of Assignor's Interest
Jan 9, 2018
From: YAM, DANNY; VASQUEZ, JORGE; CORDERO, ROBERTO; WOLF, GEORG
To: SPIN TRANSFER TECHNOLOGIES, INC.
Reel/Frame 044578/0250 →
Assignment of Assignor's Interest
Jul 16, 2018
From: BERGER, NEAL; LOUIE, BENJAMIN; EL BARAJI, MOURAD; CRUDELE, LESTER
To: SPIN TRANSFER TECHNOLOGIES, INC.
Reel/Frame 046362/0734 →
Assignment of Assignor's Interest
Jul 17, 2018
From: CRUDELE, LESTER
To: SPIN TRANSFER TECHNOLOGIES, INC.
Reel/Frame 046375/0631 →
Assignment of Assignor's Interest
Aug 13, 2019
From: HOANG, LOC
To: SPIN MEMORY, INC.
Reel/Frame 050042/0412 →
Assignment of Assignor's Interest
Jul 20, 2021
From: SPIN MEMORY, INC.
To: SPIN (ASSIGNMENT FOR THE BENEFIT OF CREDITORS), LLC
Reel/Frame 056927/0038 →
Assignment of Assignor's Interest
Sep 11, 2021
From: SPIN (ASSIGNMENT FOR BENEFIT OF CREDITORS), LLC
To: INTEGRATED SILICON SOLUTION, (CAYMAN) INC.
Reel/Frame 057473/0319 →