Patent Assignment
Reel/Frame 057473/0319
Assignment of Assignor's Interest
Recorded: 2021-09-11
Pages: 33
Assignor
SPIN (ASSIGNMENT FOR BENEFIT OF CREDITORS), LLC
Executed: 2021-08-21
Assignee
INTEGRATED SILICON SOLUTION, (CAYMAN) INC.
P.O. BOX 309, UGLAND HOUSE, GRAND CAYMAN, KY1-1104, CAYMAN ISLANDS
Covered Properties
(164)
Method for Manufacturing Mtj Memory Device
Magnetic Tunnel Junction Structure for Mram Device
Precessional Spin Current Structure for Mram
Spin Transfer Torque Structure for Mram Devices Having a Spin Current Injection Capping Layer
Method for Manufacturing Mtj Memory Device
High Annealing Temperature Perpendicular Magnetic Anisotropy Structure for Magnetic Random Access Memory
Polishing Stop Layer(S) for Processing Arrays of Semiconductor Elements
Spin Transfer Torque Mram Device with Error Buffer
Patent:
10,115,446 →
Application:
15/132,544 →
Memory Cell Having Magnetic Tunnel Junction and Thermal Stability Enhancement Layer
Method and Apparatus for Bipolar Memory Write-Verify
Device with Dynamic Redundancy Registers
Precessional Spin Current Structure with High in-Plane Magnetization for Mram
Precessional Spin Current Structure with Non-Magnetic Insertion Layer for Mram
Mram with Reduced Stray Magnetic Fields
Patent:
10,032,978 →
Application:
15/634,629 →
Memory Cell Having Magnetic Tunnel Junction and Thermal Stability Enhancement Layer
Spin Transfer Torque Structure for Mram Devices Having a Spin Current Injection Capping Layer
Polishing Stop Layer(S) for Processing Arrays of Semiconductor Elements
Method and Apparatus for Bipolar Memory Write-Verify
On-The-Fly Bit Failure Detection and Bit Redundancy Remapping Techniques to Correct for Fixed Bit Defects
Precessional Spin Current Structure for Mram
Method of Reading Data from a Memory Device Using Multiple Levels of Dynamic Redundancy Registers
A Memory Device Using Levels of Dynamic Redundancy Registers for Writing a Data Word That Failed a Write Operation
Predicting Tunnel Barrier Endurance Using Redundant Memory Structures
Patent:
10,236,075 →
Application:
15/851,593 →
A Method of Processing Incomplete Memory Operations in a Memory Device During a Power Up Sequence and a Power Down Sequence Using a Dynamic Redundancy Register
Method of Flushing the Contents of a Dynamic Redundancy Register to a Secure Storage Area During a Power Down in a Memory Device
Method of Writing Contents in Memory During a Power Up Sequence Using a Dynamic Redundancy Register in a Memory Device
Shared Bit Line Array Architecture for Magnetoresistive Memory
Memory Instruction Pipeline with a Pre-Read Stage for a Write Operation for Reducing Power Consumption in a Memory Device That Uses Dynamic Redundancy Registers
Magnetic Field Transducer Mounting Apparatus for MTJ Device Testers
Magnet Mounting Apparatus for MTJ Device Testers
Memory Instruction Pipeline with an Additional Write Stage in a Memory Device That Uses Dynamic Redundancy Registers
Smart Cache Design to Prevent Overflow for a Memory Device with a Dynamic Redundancy Register
Forcing Bits as Bad to Widen the Window Between the Distributions of Acceptable High and Low Resistive Bits Thereby Lowering the Margin and Increasing the Speed of the Sense Amplifiers
Forcing Stuck Bits, Waterfall Bits, Shunt Bits and Low Tmr Bits to Short During Testing and Using on-the-Fly Bit Failure Detection and Bit Redundancy Remapping Techniques to Correct Them
Memory Device with a Plurality of Memory Banks Where Each Memory Bank Is Associated with a Corresponding Memory Instruction Pipeline and a Dynamic Redundancy Register
Over-Voltage Write Operation of Tunnel Magnet-Resistance ("Tmr") Memory Device and Correcting Failure Bits Therefrom by Using on-the-Fly Bit Failure Detection and Bit Redundancy Remapping Techniques
Memory Device with a Dual Y-Multiplexer Structure for Performing Two Simultaneous Operations on the Same Row of a Memory Bank
Steep Slope Field-Effect Transistor (Fet) for a Perpendicular Magnetic Tunnel Junction (Pmtj)
Patent:
10,243,021 →
Application:
15/855,953 →
Perpendicular Source and Bit Lines for an Mram Array
Memory Array with Horizontal Source Line and a Virtual Source Line
Memory Array with Horizontal Source Line and Sacrificial Bitline Per Virtual Source
Memory Array with Individually Trimmable Sense Amplifiers
Process for Improving Photoresist Pillar Adhesion During Mram Fabrication
Process for Hard Mask Development for Mram Pillar Formation Using Photolithography
Fabrication Methods of Forming Cylindrical Vertical Si Etched Channel 3D Switching Devices
Process for Creating Dense Pillars Using Multiple Exposures for Mram Fabrication
Methods of Forming Perpendicular Magnetic Tunnel Junction Memory Cells Having Vertical Channels
Cylindrical Vertical Si Etched Channel 3D Switching Devices
Three-Dimensional Magnetic Memory Devices
Multi-Port Random Access Memory
Methods of Fabricating Three-Dimensional Magnetic Memory Devices
Spin Hall Effect (SHE) Assisted Three-Dimensional Spin Transfer Torque Magnetic Random Access Memory (STT-MRAM)
Ac Current Pre-Charge Write-Assist in Orthogonal Stt-Mram
Self-Generating Ac Current Assist in Orthogonal Stt-Mram
Patent:
10,270,027 →
Application:
15/858,988 →
Shared Oscillator (Stno) for Mram Array Write-Assist in Orthogonal Stt-Mram
Patent:
10,236,047 →
Application:
15/859,015 →
Ac Current Write-Assist in Orthogonal Stt-Mram
Patent:
10,236,048 →
Application:
15/859,030 →
Perpendicular Magnetic Tunnel Junction Memory Cells Having Shared Source Contacts
Three-Terminal Mram with Ac Write-Assist for Low Read Disturb
Patent:
10,199,083 →
Application:
15/859,047 →
Method of Making a Three Dimensional Perpendicular Magnetic Tunnel Junction with Thin-Film Transistor
Flexible Substrate for Use with a Perpendicular Magnetic Tunnel Junction (Pmtj)
Three Dimensional Perpendicular Magnetic Junction with Thin-Film Transistor
Magnetic Tunnel Junction (Mtj) Fabrication Methods and Systems
Vertical Steep-Slope Field-Effect Transistor (I-MOSFET) with Offset Gate Electrode for Driving a Perpendicular Magnetic Tunnel Junction (PMTJ)
Magnetic Memory having a Pinning Synthetic Antiferromagnetic Structure (SAF) with Cobalt over Platinum (Pt/Co) Bilayers
Memory Device having Overlapping Magnetic Tunnel Junctions in Compliance with a Reference Pitch
Magnetic Tunnel Junction (Mtj) Memory Device Having a Composite Free Magnetic Layer
Methods for Manufacturing a Perpendicular Magnetic Tunnel Junction (p-MTJ) MRAM having a Precessional Spin Current Injection (PSC) Structure
Method for Manufacturing a Magnetic Memory Device by Pre-Patterning a Bottom Electrode prior to Patterning a Magnetic Material
Perpendicular Magnetic Anisotropy Interface Tunnel Junction Devices and Methods of Manufacture
Fabrication Methods of Forming Annular Vertical Si Etched Channel Mos Devices
Perpendicular Magnetic Tunnel Junction Retention and Endurance Improvement
Methods of Manufacturing Magnetic Tunnel Junction Devices
Precessional Spin Current Magnetic Tunnel Junction Devices and Methods of Manufacture
Annular Vertical Si Etched Channel Mos Devices
Magnetic Tunnel Junction Devices Including an Optimization Layer
Systems and Methods Utilizing Serial Configurations of Magnetic Memory Devices
Methods and Systems for Writing to Magnetic Memory Devices Utilizing Alternating Current
Systems and Methods Utilizing Parallel Configurations of Magnetic Memory Devices
Switching and Stability Control for Perpendicular Magnetic Tunnel Junction Device
Patent:
10,236,439 →
Application:
15/859,374 →
Perpendicular Magnetic Tunnel Junction Device with Offset Precessional Spin Current Layer
Patent:
10,141,499 →
Application:
15/859,379 →
Perpendicular Magnetic Tunnel Junction Device with Precessional Spin Current Layer Having a Modulated Moment Density
Perpendicular Magnetic Tunnel Junction Device with Skyrmionic Assist Layers for Free Layer Switching
Antiferromagnetic Exchange Coupling Enhancement in Perpendicular Magnetic Tunnel Junction Stacks for Magnetic Random Access Memory Applications
Method for Combining Nvm Class and Sram Class Mram Elements on the Same Chip
Patent:
10,211,395 →
Application:
15/859,451 →
Vertically-Strained Silicon Device for Use with a Perpendicular Magnetic Tunnel Junction (Pmtj)
Magnetic Random Access Memory with Reduced Internal Operating Temperature Range
Method for Manufacturing High Density Magnetic Random Access Memory Devices Using Diamond Like Carbon Hard Mask
Perpendicular Magnetic Tunnel Junction Having Improved Reference Layer Stability
Method for Manufacturing Reduced Pitch Magnetic Random Access Memory Pillar
Method for Measuring Proximity Effect on High Density Magnetic Tunnel Junction Devices in a Magnetic Random Access Memory Device
Method for Manufacturing Magnetic Tunnel Junction Pillars Using Photolithographically Directed Block Copolymer Self-Assembly and Organometallic Gas Infusion
Microwave Write-Assist in Orthogonal Stt-Mram
Patent:
10,255,962 →
Application:
15/859,514 →
Microwave Write-Assist in Series-Interconnected Orthogonal Stt-Mram Devices
Patent:
10,229,724 →
Application:
15/859,517 →
Magnetic Random Access Memory Having Improved Reliability Through Thermal Cladding
Patent:
10,186,308 →
Application:
15/862,495 →
Perpendicular Magnetic Tunnel Junction Device with Skyrmionic Enhancement Layers for the Precessional Spin Current Magnetic Layer
Fabrication of a Perpendicular Magnetic Tunnel Junction (Pmtj) Using Block Copolymers
Buried Tap for a Vertical Transistor Used with a Perpendicular Magnetic Tunnel Junction (Pmtj)
Patent:
10,186,551 →
Application:
15/865,109 →
Methods of Fabricating Contacts for Cylindrical Devices
Patent:
10,192,787 →
Application:
15/865,123 →
Adjustable Current Selectors
Patent:
10,319,424 →
Application:
15/865,125 →
Methods of Fabricating Dual Threshold Voltage Devices with Stacked Gates
Patent:
10,192,788 →
Application:
15/865,132 →
Dual Threshold Voltage Devices Having a First Transistor and a Second Transistor
Dual Threshold Voltage Devices with Stacked Gates
Patent:
10,192,984 →
Application:
15/865,138 →
Methods of Fabricating Dual Threshold Voltage Devices
Patent:
10,192,789 →
Application:
15/865,140 →
Dual Gate Memory Devices
Methods of Fabricating Magnetic Tunnel Junctions Integrated with Selectors
Devices Including Magnetic Tunnel Junctions Integrated with Selectors
Method for Manufacturing a Chemical Guidance Pattern for Block Copolymer Self Assembly from Photolithographically Defined Topographic Block Copolymer Guided Self Assembly
Patent:
10,305,031 →
Application:
15/866,362 →
Method for Manufacturing High Density Magnetic Tunnel Junction Devices Using Photolithographic Vias and Chemically Guided Block Copolymer Self Assembly
Patent:
10,312,435 →
Application:
15/866,370 →
Dual Channel/Gate Vertical Field-Effect Transistor (Fet) for Use with a Perpendicular Magnetic Tunnel Junction (Pmtj)
Method for Manufacturing a Magnetic Memory Element Array Using High Angle Side Etch to Open Top Electrical Contact
Magnetic Tunnel Junction Wafer Adaptor Used in Magnetic Annealing Furnace and Method of Using the Same
Magnetic Tunnel Junction Wafer Adaptor Used in Magnetic Annealing Furnace and Method of Using the Same
Process for Creating a High Density Magnetic Tunnel Junction Array Test Platform
Patent:
10,411,185 →
Application:
15/992,815 →
Precessional Spin Current Structure for MRAM
Multi-Bit Cell Read-Out Techniques
Read-Out Techniques for Multi-Bit Cells
Patterning of High Density Small Feature Size Pillar Structures
Magnetic Tunnel Junction Memory Element with Improved Reference Layer Stability for Magnetic Random Access Memory Application
Three-Dimensional Arrays with Magnetic Tunnel Junction Devices Including an Annular Discontinued Free Magnetic Layer and a Planar Reference Magnetic Layer
Bit Line Structures for Three-Dimensional Arrays with Magnetic Tunnel Junction Devices Including an Annular Free Magnetic Layer and a Planar Reference Magnetic Layer
Three-Dimensional (3D) Magnetic Memory Device comprising a Magnetic Tunnel Junction (MTJ) having a Metallic Buffer Layer
System for a Wide Temperature Range Nonvolatile Memory
Method of Optimizing Write Voltage Based on Error Buffer Occupancy
Three-Dimensional Arrays with MTJ Devices Including a Free Magnetic Trench Layer and a Planar Reference Magnetic Layer
Multi-Bit Cell Read-Out Techniques for Mram Cells with Mixed Pinned Magnetization Orientations
Multi-Bit Cell Read-Out Techniques for Mram Cells with Mixed Pinned Magnetization Orientations
Memory Cell Having Magnetic Tunnel Junction and Thermal Stability Enhancement Layer
Word Line Decoder Memory Architecture
Magnetic Memory Element with Voltage Controlled Magnetic Anistropy
Defect Injection Structure and Mechanism for Magnetic Memory
Defect Propagation Structure and Mechanism for Magnetic Memory
Multi Terminal Device Stack Formation Methods
Memory System Utilizing Heterogeneous Magnetic Tunnel Junction Types in a Single Chip
Adjustable Stabilizer/Polarizer Method for MRAM with Enhanced Stability and Efficient Switching
Patent:
10,580,827 →
Application:
16/192,972 →
Spin Transfer Torque Structure for MRAM Devices Having a Spin Current Injection Capping Layer
Method for Manufacturing a Data Recording System Utilizing Heterogeneous Magnetic Tunnel Junction Types in a Single Chip
Process for Manufacturing Scalable Spin-Orbit Torque (Sot) Magnetic Memory
Spin-Orbit Torque (Sot) Magnetic Memory with Voltage or Current Assisted Switching
Patent:
10,600,465 →
Application:
16/223,080 →
Scalable Spin-Orbit Torque (SOT) Magnetic Memory
Patent:
10,658,021 →
Application:
16/223,084 →
Methods of Forming Perpendicular Magnetic Tunnel Junction Memory Cells Having Vertical Channels
High Density Mram Integration
High Density Mram Integration
Methods of Fabricating Dual Threshold Voltage Devices
Multi-Chip Module for Mram Devices with Levels of Dynamic Redundancy Registers.
Master Slave Level Shift Latch for Word Line Decoder Memory Architecture
Mram Array Having Reference Cell Structure and Circuitry That Reinforces Reference States by Induced Magnetic Field
Error Recovery in Magnetic Random Access Memory After Reflow Soldering
Process for Creating a High Density Magnetic Tunnel Junction Array Test Platform
Method for Manufacturing a Magnetic Memory Element Using Ru and Diamond Like Carbon Hard Masks
Method for Manufacturing Magnetic Memory Element with Post Pillar Formation Annealing
Adjustable Current Selectors
Vertical Selector Stt-Mram Architecture
Patent:
10,840,298 →
Application:
16/457,544 →
Systems and Methods Utilizing Serial and Parallel Configurations of Magnetic Memory Devices
Memory Array with Individually Trimmable Sense Amplifiers
Integration of Epitaxially Grown Channel Selector with Mram Device
Measurement of Mtj in a Compact Memory Array
Magnetic Tunnel Junction Wafer Adaptor Used in Magnetic Annealing Furnace and Method of Using the Same
Method of Manufacturing High Annealing Temperature Perpendicular Magnetic Anisotropy Structure for Magnetic Random Access Memory
Bi-Polar Write Scheme
Mram Noise Mitigation for Write Operations with Simultaneous Background Operations
Mram Noise Mitigation for Background Operations by Delaying Verify Timing
Determining an Inactive Memory Bank During an Idle Memory Cycle to Prevent Error Cache Overflow
Integration of Epitaxially Grown Channel Selector with Two Terminal Resistive Switching Memory Element
Vertical Selector Stt-Mram Architecture
Patent:
10,854,255 →
Application:
16/691,448 →
Related Assignments
(24)
Other recorded transfers of the patents in this record — the chain of ownership.
Assignment of Assignor's Interest
Aug 7, 2014
From: PINARBASI, MUSTAFA
To: SPIN TRANSFER TECHNOLOGIES, INC.
Reel/Frame 033488/0201 →
Assignment of Assignor's Interest
Oct 3, 2014
From: PINARBASI, MUSTAFA; KARDASZ, BARTEK
To: SPIN TRANSFER TECHNOLOGIES, INC.
Reel/Frame 033888/0498 →
Assignment of Assignor's Interest
Sep 10, 2015
From: PINARBASI, MUSTAFA MICHAEL; TZOUFRAS, MICHAIL
To: SPIN TRANSFER TECHNOLOGIES, INC.
Reel/Frame 036535/0976 →
Assignment of Assignor's Interest
Sep 25, 2015
From: KARDASZ, BARTLOMIEJ ADAM; PINARBASI, MUSTAFA MICHAEL
To: SPIN TRANSFER TECHNOLOGIES, INC.
Reel/Frame 036661/0882 →
Assignment of Assignor's Interest
Feb 11, 2016
From: PINARBASI, MUSTAFA
To: SPIN TRANSFER TECHNOLOGIES, INC.
Reel/Frame 037712/0745 →
Assignment of Assignor's Interest
Apr 6, 2016
From: KARDASZ, BARTLOMIEJ ADAM; PINARBASI, MUSTAFA MICHAEL; HERNANDEZ, JACOB ANTHONY
To: SPIN TRANSFER TECHNOLOGIES, INC.
Reel/Frame 038206/0114 →
Assignment of Assignor's Interest
Apr 13, 2016
From: PINARBASI, MUSTAFA MICHAEL; HERNANDEZ, JACOB ANTHONY; DATTA, ARINDOM; GAJEK, MARCIN JAN
To: SPIN TRANSFER TECHNOLOGIES, INC.
Reel/Frame 038267/0113 →
Assignment of Assignor's Interest
Apr 19, 2016
From: LOUIE, BENJAMIN STANLEY; BERGER, NEAL
To: SPIN TRANSFER TECHNOLOGIES, INC.
Reel/Frame 038318/0318 →
Assignment of Assignor's Interest
May 18, 2016
From: PINARBASI, MUSTAFA; KARDASZ, BARTEK
To: SPIN TRANSFER TECHNOLOGIES, INC.
Reel/Frame 038635/0055 →
Assignment of Assignor's Interest
Jun 6, 2016
From: BERGER, NEAL; LOUIE, BEN; EL-BARAJI, MOURAD
To: SPIN TRANSFER TECHNOLOGIES, INC.
Reel/Frame 038820/0643 →
Assignment of Assignor's Interest
Sep 27, 2016
From: EL BARAJI, MOURAD; BERGER, NEAL; LOUIE, BENJAMIN STANLEY; CRUDELE, LESTER M.
To: SPIN TRANSFER TECHNOLOGIES, INC.
Reel/Frame 039870/0697 →
Assignment of Assignor's Interest
Feb 28, 2017
From: PINARBASI, MUSTAFA MICHAEL; KARDASZ, BARTLOMIEJ ADAM
To: SPIN TRANSFER TECHNOLOGIES, INC.
Reel/Frame 041402/0487 →
Assignment of Assignor's Interest
Feb 28, 2017
From: PINARBASI, MUSTAFA MICHAEL; KARDASZ, BARTLOMIEJ ADAM
To: SPIN TRANSFER TECHNOLOGIES, INC.
Reel/Frame 041401/0881 →
Security Interest
Jun 16, 2017
From: SPIN TRANSFER TECHNOLOGIES, INC.
To: SILICON VALLEY BANK
Reel/Frame 042981/0819 →
Assignment of Assignor's Interest
Jun 27, 2017
From: SCHABES, MANFRED ERNST; KARDASZ, BARTLOMIEJ ADAM; PINARBASI, MUSTAFA
To: SPIN TRANSFER TECHNOLOGIES, INC.
Reel/Frame 042829/0320 →
Assignment of Assignor's Interest
Jul 21, 2017
From: PINARBASI, MUSTAFA; KARDASZ, BARTEK
To: SPIN TRANSFER TECHNOLOGIES, INC.
Reel/Frame 043065/0347 →
Assignment of Assignor's Interest
Jul 24, 2017
From: KARDASZ, BARTLOMIEJ ADAM; PINARBASI, MUSTAFA MICHAEL
To: SPIN TRANSFER TECHNOLOGIES, INC.
Reel/Frame 043075/0511 →
Assignment of Assignor's Interest
Aug 11, 2017
From: PINARBASI, MUSTAFA MICHAEL; HERNANDEZ, JACOB ANTHONY; DATTA, ARINDOM; GAJEK, MARCIN JAN
To: SPIN TRANSFER TECHNOLOGIES, INC.
Reel/Frame 043266/0001 →
Assignment of Assignor's Interest
Oct 20, 2017
From: KARDASZ, BARTLOMIEJ ADAM
To: SPIN TRANSFER TECHNOLOGIES, INC.
Reel/Frame 043915/0198 →
Assignment of Assignor's Interest
Nov 25, 2017
From: HOBERMAN, BARRY
To: SPIN TRANSFER TECHNOLOGIES, INC.
Reel/Frame 044219/0987 →
Change of Name
Jan 15, 2019
From: SPIN TRANSFER TECHNOLOGIES, INC.
To: SPIN MEMORY, INC.
Reel/Frame 048075/0550 →
Change of Name
Jun 10, 2019
From: SPIN TRANSFER TECHNOLOGIES, INC.
To: SPIN MEMORY, INC.
Reel/Frame 049421/0501 →
Assignment of Assignor's Interest
Jul 20, 2021
From: SPIN MEMORY, INC.
To: SPIN (ASSIGNMENT FOR THE BENEFIT OF CREDITORS), LLC
Reel/Frame 056927/0038 →
Assignment of Assignor's Interest
Sep 7, 2021
From: SPIN (ASSIGNMENT FOR BENEFIT OF CREDITORS), LLC
To: INTEGRATED SILICON SOLUTION, (CAYMAN) INC.
Reel/Frame 057436/0237 →