Adjustable current selectors
The various implementations described herein include methods, devices, and systems for performing operations on memory devices. In one aspect, a memory device a magnetic memory component and a current selector component coupled to the magnetic memory component. The current selector component includes a first transistor having a first gate with a corresponding first threshold voltage. The first transistor comprises a charge storage layer configured to selectively store charge so as to adjust a current through the first transistor. The memory device further includes control circuitry configured to determine a bit error rate of the magnetic memory component and adjust a charge stored in the charge storage layer based on the determined bit error rate.
1. A memory device, comprising:
a magnetic memory component;
a current selector component coupled to the magnetic memory component, the current selector component comprising a first transistor having a first gate with a corresponding first threshold voltage, wherein the first transistor comprises a charge storage layer configured to selectively store charge so as to adjust a current through the first transistor;
control circuitry configured to:
determine a bit error rate of the magnetic memory component; and
adjust a charge stored in the charge storage layer based on the determined bit error rate; and
a first wordline and a second wordline, wherein the first gate is coupled to the first wordline.
2. The memory device of claim 1 , further comprising a source line; and
wherein the magnetic memory component is coupled to the source line via the current selector component.
3. The memory device of claim 1 , wherein the current selector component is configured to selectively supply a plurality of currents to the magnetic memory component.
4. The memory device of claim 3 , wherein the plurality of currents corresponds to a plurality of current thresholds for reading and writing to the magnetic memory component.
5. The memory device of claim 3 , wherein the control circuitry is configured to select a particular current of the plurality of currents based on a temperature of the magnetic memory component.
6. The memory device of claim 3 , wherein the control circuitry is configured to select a particular current of the plurality of currents based on a desired error rate for the magnetic memory component.
7. The memory device of claim 1 , wherein the charge storage layer is a floating gate or charge trap.
8. The memory device of claim 1 , wherein the control circuitry is configured to repeat the determining and the adjusting until the determined bit error rate is within a desired bit error range.
9. The memory device of claim 1 , further comprising a bitline, wherein the current selector component is coupled to the bitline via the magnetic memory component.
10. The memory device of claim 9 , wherein the current selector component is further coupled to the bitline via bypass circuitry configured to bypass the magnetic memory component.
11. The memory device of claim 9 , further comprising a program line; and
wherein the current selector component is coupled to the program line via bypass circuitry configured to selectively couple the current selector component to the program line and selectively decouple the magnetic memory component from the current selector component.