Method of making a three dimensional perpendicular magnetic tunnel junction with thin-film transistor

1. A method of forming a magnetic memory device, the method comprising:

forming a source region above a substrate, the source region comprising a first semiconductor material having a first conductivity;

forming an array of three-dimensional structures above the substrate, wherein the forming comprises:

forming layers above the source region in an order as follows: a first buffer layer, a dielectric layer, a second buffer layer, a first perpendicular-magnetic tunnel junction sensor, a third buffer layer, a n th perpendicular-magnetic tunnel junction sensor, a (n+2) th buffer layer; and

defining an array of three-dimensional structures in the formed layers, wherein each three-dimensional structure comprises a stack of formed layers in a vertical direction above the substrate, wherein each three-dimensional structure has a bottom at the substrate, a top, and a sidewall extending between the bottom and the top, wherein a cavity region is formed between the sidewall of each adjacent three-dimensional structure;

depositing a channel material on a surface of at least one sidewall of each three-dimensional structure;

depositing a gate dielectric material on the channel material on the surface of at least one sidewall of each three dimensional structure;

forming a first isolation region in the cavity region above the substrate;

forming a first gate region above the first isolation region in the cavity region; and

forming a second isolation region above the first gate region, wherein a n th gate region is formed above a (n+1) isolation region thereafter until a top of the array of three-dimensional structures, wherein each n th gate region is coupled to each n th perpendicular magnetic tunnel junction sensor of each three-dimensional structure.

2. A method as recited in claim 1 , wherein the first conductivity of the semiconductor material of each source region is a metal.

3. A method as recited in claim 1 , wherein the first conductivity of the semiconductor material of each source region is a n-type conductivity.

4. A method as recited in claim 1 , wherein the n th layers of a perpendicular-magnetic junction sensor comprises:

a seed layer;

an underlayer;

a synthetic antiferromagnetic seed layer;

a synthetic antiferromagnetic layer

an antiferromagnetic coupling layer;

a ferromagnetic coupling layer;

a reference layer;

a barrier layer;

a free layer; and

a capping layer.

5. A method as recited in claim 1 , wherein a thickness of each n th gate region is at least a thickness of each n th perpendicular magnetic tunnel junctions sensor of each three-dimensional structure.

6. A method as recited in claim 1 , wherein the dielectric layer is selected from a group consisting of: SiO 2 , Si 3 N 4 , HfO 2 , or Al 2 O 3 .

7. A method as recited in claim 1 , wherein each buffer layer is selected from the group consisting of: TaN, TiN, W, and Ru.

8. A method as recited in claim 1 , wherein each gate region comprises a second semiconductor material having a second conductivity.

9. A method as recited in claim 1 , wherein each gate region comprises at least one metal material selected from the group consisting of: W, TaN, TiN, and Ru.

10. A method as recited in claim 1 , wherein forming the layers of the three-dimensional structures includes thin-film deposition using at least one of: atomic layer deposition and plasma-enhanced chemical vapor deposition.

11. A method as recited in claim 1 , wherein a final layer formed above the substrate is a hardmask layer.

12. A method as recited in claim 1 , wherein defining the array of three-dimensional structures includes at least one of: wet chemical etching, ion beam etching, and plasma etching.

13. A method as recited in claim 1 , wherein depositing the channel material includes at least one of: thermal/e-beam evaporator, radio frequency magnetron sputtering, metal oxide chemical vapor deposition, and atomic layer deposition.

14. A method as recited in claim 1 , wherein depositing the gate dielectric material includes atomic layer deposition.

15. A method as recited in claim 1 , wherein each gate region is coupled to at least one sidewall of adjacent three dimensional structures.

16. A method as recited in claim 1 , wherein each n th gate region is coupled to the n th perpendicular magnetic tunnel junction sensor of each three-dimensional structure in an x-direction of the array of three-dimensional structures.

17. A method as recited in claim 1 , wherein each three dimensional structure in a single column in a y-direction is a connected by a sourceline/bitline.

18. A method as recited in claim 1 , wherein each three-dimensional structure in a single row in an x-direction is connected by a wordline of each gate region.

19. A method as recited in claim 1 , wherein forming each gate region alternately with each isolation region includes bottom up processes.

20. A method as recited in claim 1 , wherein the isolation region may include silicon dioxide.

21. A method as recited in claim 1 , wherein the array of three-dimensional structures may be formed on a substrate using for back-end-of-line processes.

22. A method as recited in claim 21 , wherein a method for forming the substrate comprises:

recessing a portion between each k th level source region having a first conductivity of a substrate;

forming a layer of silicon material above the substrate, wherein the layer of silicon material is amorphous;

depositing an oxide material above the layer of silicon material;

planarizing a surface of the substrate to each k th level source region; and

annealing a surface of the substrate.

23. A method as recited in claim 22 wherein the portion recessed is silicon dioxide.

24. A method as recited in claim 22 , wherein the surface of the substrate has a single crystalline silicon structure.