Method for manufacturing a magnetic memory device by pre-patterning a bottom electrode prior to patterning a magnetic material
A method for manufacturing a magnetic random access memory element that allows for improved magnetic element pillar formation in a high density magnetic memory element array. The method allows a magnetic memory element pillar to be formed by ion milling with a lower pillar height for reduced shadowing effect. A memory element seed layer and under-layer are first formed on a substrate and layer of electrically insulating material such as silicon oxide is deposited. A chemical mechanical polishing process is performed, leaving the seed layer and under-layer surrounded by a layer of electrically insulating material having an upper surface that is coplanar with an upper surface of the under-layer. A magnetic memory element pillar is formed over the seed layer and under-layer by depositing the magnetic memory element material, forming a mask over the magnetic memory element material and performing an ion milling process to form a magnetic memory element pillar.
1. A method for manufacturing a magnetic memory device, the method comprising:
depositing a seed layer;
depositing an under-layer over the seed layer;
forming a mask structure over the under-layer, the mask structure being configured to cover a magnetic device area;
performing an etching process to remove portions of the under-layer and seed layer that are not protected by the mask;
depositing an electrically insulating layer;
performing a chemical mechanical polishing (CMP) sufficiently to expose the under-layer;
after performing the CMP, depositing a thin layer of under-layer material by sputter deposition to a thickness no greater than 3 Angstroms; and
forming a magnetic memory element pillar over the under-layer.
2. The method as in claim 1 , wherein the forming a magnetic memory element pillar further comprises:
depositing a magnetic memory element material;
forming a magnetic memory element defining mask over the magnetic memory element material; and
performing an ion milling.
3. The method as in claim 2 , wherein the ion milling is performed at an angle relative to normal.
4. The method as in claim 1 , wherein the electrically insulating layer comprises silicon oxide.
5. The method as in claim 1 , further comprising after performing the CMP, depositing a thin layer of under-layer material over the under-layer.
6. The method as in claim 1 , wherein the seed layer comprises tantalum.
7. The method as in claim 1 , wherein the chemical mechanical polishing is performed sufficiently to form coplanar upper surfaces for the under-layer and the electrically insulating layer.
8. The method as in claim 1 , wherein the seed layer is deposited on a substrate that includes electrically conductive electrodes separated by dielectric layers and wherein the mask is formed to cover areas over the electrically conductive electrodes and leave areas over the dielectric layers uncovered.
9. The method as in claim 1 , wherein the electrically insulating layer comprises silicon oxide deposited by sputter deposition.
10. The method as in claim 1 , wherein the electrically insulating layer is deposited to a thickness that extends to a top surface of the under-layer.
11. The method as in claim 1 , wherein the under-layer comprises ruthenium and has a thickness of 30 angstroms.
12. The method as in claim 1 , wherein the seed layer comprises tantalum and has a thickness of 10 angstroms.
13. The method as in claim 1 , wherein the magnetic memory element pillar comprises a magnetic reference layer, a non-magnetic barrier layer and a magnetic free layer.