IP Library Granted Patent US 10,930,843
Granted Patent B2
US 10,930,843 · App. 16/223,077 · Granted Feb 23, 2021

Process for manufacturing scalable spin-orbit torque (SOT) magnetic memory

Inventor: Satoru Araki (San Jose, CA)
Assignee: SPIN MEMORY, INC.
H01L43/14G11C11/161H01L27/228H01L43/04H01L43/065G11C11/1655G11C11/1657G11C11/1673G11C11/1675
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Quick Facts
Patent No.
US 10,930,843
App. No.
16/223,077
Granted
Feb 23, 2021
Kind
B2
Abstract

A method of fabricating a magnetic storage device includes depositing a first conductive material. The method further includes electrically isolating distinct instances of the first conductive material to form a first wire extending along a first direction. The method further includes depositing, on the distinct instances of the first conductive material, a set of device layers. The method further includes electrically isolating distinct instances of the device layers to form spin orbit torque magnetic random access memory (SOT-MRAM) devices positioned on distinct instances of the first conductive material. The method further includes depositing, on the distinct instances of the device layers, a layer of a second conductive material and electrically isolating a plurality of distinct instances of the layer of the second conductive material to form a plurality of second wires extending along a second direction. The second direction is different from the first direction.

Claims (21)

1. A method of fabricating a magnetic storage device, comprising:

depositing a layer of a first conductive material;

electrically isolating a plurality of distinct instances of the layer of the first conductive material to form a plurality of first wires extending along a first direction;

depositing, on the plurality of distinct instances of the layer of the first conductive material, a common set of device layers;

electrically isolating distinct instances of the common set of device layers to form a plurality of spin orbit torque magnetic random access memory (SOT-MRAM) devices, wherein each SOT-MRAM device of the plurality of SOT-MRAM devices is positioned on a distinct instance of the layer of the first conductive material;

depositing, on the distinct instances of the common set of device layers, a layer of a second conductive material; and

electrically isolating a plurality of distinct instances of the layer of the second conductive material to form a plurality of second wires extending along a second direction, wherein the second direction is different from the first direction.

2. The method of claim 1 , wherein electrically isolating the distinct instances of the common set of device layers comprises etching the common set of device layers into lines extending in the second direction.

3. The method of claim 2 , wherein electrically isolating the distinct instances of the common set of device layers further comprises destroying the conductivity of portions of each line without etching the portions of each line to form conductive pillars from each line, wherein each SOT-MRAM device comprises a conductive pillar.

4. The method of claim 3 , further including, prior to destroying the conductivity of portions of each line without etching the portions of each line:

depositing a protective layer over the line; and

patterning the protective layer to expose the portions of the line.

5. The method of claim 2 , wherein each distinct instance of the layer of the second conductive material is coincident with a respective line extending in the second direction.

6. The method of claim 1 , wherein electrically isolating the distinct instances of the common set of device layers comprises etching the common set of device layers into lines extending in the first direction.

7. The method of claim 6 , wherein each distinct instance of the layer of the first conductive material is coincident with a respective line extending in the first direction.

8. The method of claim 2 , wherein the etching comprises a reactive ion etch.

9. The method of claim 8 , wherein the reactive ion etch is based on a carbonyl chemistry.

10. The method of claim 1 . wherein the common set of device layers is deposited after electrically isolating the plurality of distinct instances of the layer of the first conductive material.

11. The method of claim 1 , wherein the second layer of conductive material is deposited after electrically isolating the plurality of distinct instances of the layer of the first conductive material.

12. The method of claim 1 , wherein electrically isolating the plurality of distinct instances of the layer of the first conductive material comprises removing portions of the layer of first conductive material.

13. The method of claim 1 , wherein electrically isolating the plurality of distinct instances of the layer of the first conductive material comprises destroying the conductivity of portions of the layer of first conductive material without removing the portions of the layer of first conductive material.

Assignments (4)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 11, 2021
From: SPIN (ASSIGNMENT FOR BENEFIT OF CREDITORS), LLC
To: INTEGRATED SILICON SOLUTION, (CAYMAN) INC.
Reel/Frame 057473/0319 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 20, 2021
From: SPIN MEMORY, INC.
To: SPIN (ASSIGNMENT FOR THE BENEFIT OF CREDITORS), LLC
Reel/Frame 056927/0038 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 4, 2020
From: ARAKI, SATORU
To: SPIN TRANSFER TECHNOLOGIES
Reel/Frame 052844/0147 →
CHANGE OF NAME Recorded Jan 17, 2019
From: SPIN TRANSFER TECHNOLOGIES, INC.
To: SPIN MEMORY, INC.
Reel/Frame 048054/0173 →
Continuity (1)
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