Forcing stuck bits, waterfall bits, shunt bits and low TMR bits to short during testing and using on-the-fly bit failure detection and bit redundancy remapping techniques to correct them
A method for correcting bit defects in a memory array is disclosed. The method comprises determining, during a characterization stage, a resistance distribution for the memory array by classifying a state of each bit-cell in the memory array, wherein the memory array comprises a plurality of codewords, wherein each codeword comprises a plurality of redundant bits. Further, the method comprises determining bit-cells in the resistance distribution that are ambiguous, wherein ambiguous bit-cells have ambiguous resistances between being high or low bits. Subsequently, the method comprises forcing the ambiguous bit-cells to short circuits and replacing each short-circuited ambiguous bit-cell with a corresponding redundant bit from an associated codeword.
1. A method for correcting bit defects in a memory array, the method comprising:
determining, during a characterization stage, a resistance distribution for the memory array by classifying a state of each bit-cell in the memory array, wherein the memory array comprises a plurality of codewords, wherein each codeword comprises a plurality of redundant bits;
determining bit-cells of the resistance distribution that are ambiguous, wherein ambiguous bit-cells have ambiguous resistances;
forcing the ambiguous bit-cells to short circuits; and
replacing each short-circuited ambiguous bit-cell with a corresponding redundant bit from an associated codeword.
2. The method of claim 1 , wherein the memory array is an STT-MRAM memory array.
3. The method of claim 1 , wherein the replacing comprises:
determining a position of a short-circuited bit-cell in an associated codeword; and
mapping a corresponding redundant bit of an associated plurality of redundant bits in the associated codeword to the short-circuited bit-cell in accordance with a bit position of the short-circuited bit-cell in the associated codeword.
4. The method of claim 3 , wherein the mapping is performed in accordance with a mapping scheme.
5. The method of claim 4 , wherein in the mapping scheme a short-circuited bit-cell is replaced with a corresponding redundant bit having a position that is based on the bit position of the short-circuited bit-cell.
6. The method of claim 1 , wherein said state is chosen from a group consisting of: high, low, short or open.
7. The method of claim 1 , wherein the ambiguous bit-cells are selected from a group consisting of: stuck bits; waterfall bits; shunted bits; and low tunnel magnetoresistance (TMR) bits.
8. An apparatus for correcting bit defects, the apparatus comprising:
a processor; and
a memory array comprising a plurality of codewords, wherein each codeword comprises a respective plurality of redundant bits, and wherein the processor is configured to:
determine, during a characterization stage, a resistance distribution for the memory array by classifying a state of each bit-cell in the memory array;
determine bit-cells of the resistance distribution that are ambiguous, wherein ambiguous bit-cells have ambiguous resistances;
force the ambiguous bit-cells to short circuits; and
replace each short-circuited ambiguous bit-cell with a corresponding redundant bit from an associated codeword.
9. The apparatus of claim 8 , wherein the memory array is an STT-MRAM memory array.
10. The apparatus of claim 8 , wherein to replace each short-circuited ambiguous bit-cell, the processor is configured to:
determine a position of a short-circuited bit-cell in an associated codeword; and
map the corresponding redundant bit of an associated plurality of redundant bits of the associated codeword to the short-circuited bit-cell in accordance with the position of the short-circuited bit-cell.
11. The apparatus of claim 10 , wherein the processor is further configured to map the corresponding redundant bit in accordance with a mapping scheme.
12. The apparatus of claim 11 , wherein in the mapping scheme the short-circuited bit-cell is replaced with the corresponding redundant bit based on the position of the short-circuited bit-cell.
13. The apparatus of claim 8 , wherein said state is chosen from a group consisting of:
high, low, short or open.
14. The apparatus of claim 8 , wherein the ambiguous bit-cells are selected from a group consisting of: stuck bits; waterfall bits; shunted bits; and low tunnel magnetoresistance (TMR) bits.
15. A method for correcting bit defects in a memory, the method comprising:
determining, during a characterization stage, a resistance distribution for a memory array by classifying a state of each bit-cell in the memory array, wherein the memory array comprises a plurality of codewords, wherein each codeword comprises a plurality of redundant bit-cells;
determining bit-cells of the resistance distribution that are defective;
forcing defective bit-cells to short circuits; and
replacing each short-circuited defective bit-cell with a corresponding redundant bit-cell from an associated codeword.
16. The method of claim 15 , wherein the memory array is a STT-MRAM memory array.
17. The method of claim 15 , wherein the defective bit-cells are ambiguous bit-cells having ambiguous resistances between being high or low bits.
18. The method of claim 17 , wherein the ambiguous bit-cells are selected from a group consisting of: stuck bits; waterfall bits; shunted bits; and low tunnel magnetoresistance (TMR) bits.
19. The method of claim 15 , wherein the defective bit-cells have a substantially higher WER compared to other bit-cells in the memory array.
20. The method of claim 15 , wherein the defective bit-cells retain their data for lower than a minimum retention period.