Polishing stop layer(s) for processing arrays of semiconductor elements
Described embodiments can be used in semiconductor manufacturing and employ materials with high and low polish rates to help determine a precise polish end point that is consistent throughout a wafer and that can cease polishing prior to damaging semiconductor elements. The height of the low polish rate material between the semiconductor elements is used as the polishing endpoint. Because the low polish rate material slows down the polishing process, it is easy to determine an end point and avoid damage to the semiconductor elements. An additional or alternative etch end point can be a thin layer of material that provides a very clear spectroscopy signal when it has been exposed, allowing the etch process to cease.
1. A semiconductor device comprising:
a semiconductor wafer; a plurality of magnetic tunnel junction (MTJ) pillars thereon, each MTJ pillar comprising a plurality of layers and a hard-mask layer, the hard-mask layer having a bottom surface at a hard-mask bottom height, each MTJ pillar having a top surface and a side surface, the top surface extending at an MTJ pillar height from the wafer, the top surface of each MTJ pillar being exposed for electrical connection;
the semiconductor wafer with the plurality of MTJ pillars thereon having a first plurality of valley portions between the plurality of MTJ pillars;
a first nonmagnetic layer, the first nonmagnetic layer being comprised of a high chemical-mechanical polish (CMP) rate material, said first nonmagnetic layer comprising a first side portion over the side surface of each of the plurality of MTJ pillars and a second plurality of valley portions over the first plurality of valley portions between the plurality of MTJ pillars;
a second nonmagnetic layer, the second nonmagnetic layer being comprised of a high chemical-mechanical polish (CMP) rate material, said second nonmagnetic layer comprising a second side portion over the first side portion of the first nonmagnetic layer and a third plurality of valley portions over the second plurality of valley portions;
a third nonmagnetic layer, the third nonmagnetic layer being comprised of a high chemical-mechanical polish (CMP) rate material, said third nonmagnetic layer comprising a third side portion over the second side portion of the second nonmagnetic layer and a fourth plurality of valley portions over the third plurality of valley portions;
a fourth nonmagnetic layer, the fourth nonmagnetic layer being comprised of a high chemical-mechanical polish (CMP) rate material, said fourth nonmagnetic layer comprising a fourth side portion over the third side portion of the third nonmagnetic layer and a fifth plurality of valley portions over the fourth plurality of valley portions; and
a fifth nonmagnetic layer, the fifth nonmagnetic layer being comprised of low chemical-mechanical polish (CMP) rate material, the fifth nonmagnetic layer comprising a fifth side portion the fourth side portion of the fourth nonmagnetic layer and a sixth plurality of valley portions over the fifth plurality of valley portions, each of the plurality of sixth valley portions of the fifth nonmagnetic layer having a top surface, the fifth nonmagnetic layer having a thickness such that the top surface of each of the sixth valley portions of the fifth nonmagnetic layer has a height above the hard-mask bottom height, the low CMP rate material having a lower polish rate than the polish rate of the high CMP rate material, the fifth nonmagnetic layer being non-magnetic, wherein the side surface of each of the plurality of MTJ pillars are covered by the first nonmagnetic layer, the second nonmagnetic layer, the third nonmagnetic layer, the fourth nonmagnetic layer and the fifth nonmagnetic layer after the plurality of MTJ pillars were chemical-mechanically polished with a chemical-mechanical polisher.
2. The semiconductor device of claim 1 , wherein the fifth nonmagnetic layer has a thickness such that the top surface of each of the third valley portions of the fifth nonmagnetic layer has a height equal to the MTJ pillar height, thereby exposing top surfaces of the plurality of MTJ pillars.
3. The semiconductor device of claim 1 , wherein the fifth nonmagnetic layer has a thickness such that the top surface of each of the third valley portions of the fifth nonmagnetic layer has a height above the MTJ pillar height.
4. The semiconductor device of claim 1 , wherein the first nonmagnetic layer, the second nonmagnetic layer, the third nonmagnetic layer and the fourth nonmagnetic layer are an insulator material.
5. The semiconductor device of claim 4 , wherein the insulator material is SiOx.
6. The semiconductor device of claim 1 , wherein the fifth nonmagnetic layer is an insulator material.
7. The semiconductor device of claim 6 , wherein the insulator material is SiNx.
8. The semiconductor device of claim 1 , further comprising a sixth nonmagnetic layer, the sixth layer being comprised of the high CMP rate material, the sixth layer comprising a side portion over each side portion of the fourth nonmagnetic layer.