Methods of fabricating contacts for cylindrical devices
A device having two transistors with dual thresholds, and a method of fabricating the device, including fabricating a silicide source, a conductive layer, and contacts to a plurality of layers of the device, is provided. The device has a core and a plurality of layers that surround the core in succession, including a first layer, a second layer, a third layer, and a fourth layer. The device further comprises a first input terminal coupled to the core, the first input terminal being configured to receive a first voltage and a second input terminal coupled to the fourth layer, the second input terminal being configured to receive a second voltage. The device comprises a common source terminal coupled to the core and the fourth layer. A memory device, such as an MTJ, may be coupled to the device.
1. A method of forming a contact, comprising:
at an annular device composed of a core and a plurality of layers that surround the core in succession, the plurality of layers including a first layer and a second layer, wherein the core and the second layer are separated by the first layer:
depositing a coating on a surface of the annular device, the surface including the core and the plurality of layers;
determining relative heights of the core, the first layer, and the second layer;
in accordance with a determination that the second layer has the largest relative height:
performing a first removal of the coating to expose the second layer;
depositing a first metal on the second layer;
performing a second removal of the coating to expose the core; and
depositing a second metal on the core;
in accordance with a determination that the core has the largest relative height:
etching a portion of the coating to expose the core; and
forming a first terminal by depositing a conductive material, wherein the conductive material contacts the exposed core and the first input terminal extends radially outward from the annular device.
2. The method of claim 1 , further comprising, after forming the first input terminal, planarizing a top surface of the first input terminal to create a flat surface.
3. The method of claim 1 , wherein the first removal is a planarization process.
4. The method of claim 2 , wherein the first removal is a chemical mechanical planarization process.
5. The method of claim 1 , wherein the coating is a nitride-based coating.
6. The method of claim 1 , wherein the plurality of layers further includes a third layer and a fourth layer.
7. The method of claim 5 , wherein:
the core, the first layer, and the second layer correspond to a first transistor;
the second layer, the third layer, and the fourth layer correspond to a second transistor; and
the second layer is a channel common to the first transistor and the second transistor.
8. The method of claim 1 , wherein the first metal and the second metal are a same material type.
9. The method of claim 1 , further comprising, creating a contact to the core including:
depositing, on top of the plurality of layers, a metal gate contact material;
etching through the plurality of layers and the metal gate contact material to a first height;
depositing a first mask;
depositing a layer of silicon nitride (SiN);
depositing a second mask and etching the layer of SiN in accordance with the second mask to create a trench in the SiN; and
depositing a metal gate contact on the trench.
10. The method of claim 9 , wherein the metal gate contact material is tantalum nitride.
11. The method of claim 9 , wherein the first height is based on the height of a second highest layer of the plurality of layers.
12. The method of claim 9 , further comprising, after depositing the first mask, wet dipping the plurality of layers in potassium hydroxide in accordance with the mask.
13. The method of claim 12 , wherein the wet dipping decreases the height of the third layer and the fourth layer.
14. The method of claim 9 , wherein the layer of silicon nitride is thick SiN.
15. The method of claim 9 , further comprising, performing a chemical mechanical polishing (CMP) on the layer of SiN.