Methods of fabricating dual threshold voltage devices
A device having two transistors with dual thresholds, and a method of fabricating the device, including fabricating a silicide source, a conductive layer, and contacts to a plurality of layers of the device, is provided. The device has a core and a plurality of layers that surround the core in succession, including a first layer, a second layer, a third layer, and a fourth layer. The device further comprises a first input terminal coupled to the core, the first input terminal being configured to receive a first voltage and a second input terminal coupled to the fourth layer, the second input terminal being configured to receive a second voltage. The device comprises a common source terminal coupled to the core and the fourth layer. A memory device, such as an MTJ, may be coupled to the device.
1. A method of fabricating a cylindrical device, comprising:
providing a cylindrical device having two transistors sharing a common silicide source; and
creating the silicide source, including:
depositing multiple layers in succession on an oxidized silicon substrate, the multiple layers including at least an oxide layer and a planarization layer;
removing, at least partially, the oxide layer and the planarization layer until the silicon substrate is exposed;
removing, at least partially, the oxide layer to expose a horizontal cross section of the cylindrical device to create an annular silicon substrate area; and
after the removing, depositing a siliciding metal on the annular area to form the silicide source.
2. The method of claim 1 , further comprising:
before depositing the siliciding metal and after a source ion implant operation and removing a photoresist, performing a first rapid thermal annealing (RTA); and
after depositing the siliciding metal, performing a second RTA.
3. The method of claim 1 , wherein the annular area is at a bottom of the cylindrical device.
4. The method of claim 1 , wherein providing the cylindrical device having the two transistors comprises: (i) providing a conductive core corresponding to a first transistor of the two transistors, and (ii) forming a plurality of cylindrical layers around the conductive core, including a first dielectric layer, a second layer, a third dielectric layer, and a fourth conductive layer corresponding to a second transistor of the two transistors.
5. The method of claim 3 , wherein the second layer of the cylindrical device corresponds to a common channel of two transistors in parallel, and the common channel composed of semiconductor material.
6. The method of claim 5 , further comprising removing the siliciding metal from the second layer of the cylindrical device, wherein removing the siliciding metal leaves a residual reacted metal forming the silicide source.
7. The method of claim 4 , further comprising applying a mask after depositing the multiple layers and after removing some selectively, wherein the mask protects covered areas.
8. The method of claim 4 , wherein forming the plurality of cylindrical layers around the cylindrical core comprises:
depositing a spin-on glass (SOG) layer on a first plane of the cylindrical device to create a sloped ring around the bottom of the cylindrical device, wherein the cylindrical device is vertically disposed in the first plane and the SOG layer surrounds the cylindrical device;
etching the SOG layer from around and inside the cylindrical device to a desired depth;
depositing one or more dielectric materials to form the third dielectric layer;
depositing a doped material on the first plane, a horizontal cross section of the cylindrical device, a top of the cylindrical device, and the sloped ring;
etching the doped material on the top of the cylindrical device and on the sloped ring; and
depositing a siliciding metal to create the fourth conductive layer.
9. The method of claim 8 , further comprising performing a third RTA to finish creation of the fourth conductive layer.
10. The method of claim 9 , further comprising wet etching the unreacted siliciding metal after the third RTA.
11. The method of claim 4 , wherein:
the oxide layer is a first oxide layer; and
the method further comprises creating a contact to the second transistor of the two transistors, including:
depositing a second oxide layer to create an oxide plane;
depositing a spin-on glass (SOG) layer on the oxide plane, wherein the cylindrical device is vertically disposed in the oxide plane;
depositing an organic compound to a first height to create an organic planarization layer (OPL), wherein the OPL surrounds a horizontal cross section of the cylindrical device;
depositing a third oxide layer onto the OPL, wherein the third oxide layer surrounds a horizontal cross section of the cylindrical device;
depositing anti-reflective coating and photoresist on the third oxide layer;
removing, using a first removal technique, the anti-reflective coating and the third oxide layer,
removing, using a second removal technique, the OPL until the SOG layer is exposed, thereby forming a trench; and
depositing a metallic material in the trench to create the contact to a gate of the second transistor.
12. The method of claim 11 , further comprising etching the SOG layer to a first thickness before depositing the organic compound.
13. The method of claim 11 , wherein the first removal technique is a fluorine-based chemistry.
14. The method of claim 13 , further comprising depositing a photoresist layer on the anti-reflective coating, wherein the anti-reflective coating and the photoresist layer surround a horizontal cross section of the cylindrical device.
15. The method of claim 14 , further comprising creating a mask with the photoresist layer before removing the anti-reflective coating and the second oxide layer using the fluorine-based chemistry, wherein said removing is defined by the mask of the photoresist layer.
16. The method of claim 11 , wherein the second removal technique uses oxygen plasma to remove the OPL.
17. The method of claim 11 , wherein the metallic material is tantalum nitride.
18. The method of claim 4 , wherein the method further comprises creating a contact to the first transistor of the two transistors, including:
depositing, on top of the plurality of cylindrical layers, a metal gate contact material;
etching through the plurality of cylindrical layers and the metal gate contact material to a first height extending across the conductive core through the fourth layer;
depositing, a first mask;
depositing a layer of silicon nitride (SiN);
depositing a second mask and etching the layer of SiN in accordance with the second mask to create a flat surface; and
depositing a metal gate contact on the flat surface to create a contact to the first transistor.
19. The method of claim 18 , wherein the metal gate contact material is tantalum nitride.
20. The method of claim 18 , wherein the first height is based on the height of a second highest layer of the plurality of layers.
21. The method of claim 18 , further comprising, after depositing the first mask, wet dipping the plurality of layers in potassium hydroxide in accordance with the mask.
22. The method of claim 21 , wherein the wet dipping decreases the height of the third layer and the fourth layer.
23. The method of claim 18 , wherein the layer of silicon nitride is thick SiN.
24. The method of claim 18 , further comprising, performing a chemical mechanical polishing (CMP) on the layer of SiN.
25. The method of claim 1 , wherein the two transistors have dual threshold voltages.