Dual gate memory devices
The various implementations described herein include methods, devices, and systems for performing operations on memory devices. In one aspect, a memory device includes: (1) a first charge storage device having a first gate with a corresponding first threshold voltage, the first charge storage device configured to store charge corresponding to one or more first bits; and (2) a second charge storage device having a second gate with a corresponding second threshold voltage, distinct from the first threshold voltage, the second charge storage device configured to store charge corresponding to one or more second bits; where the second charge storage device is coupled in parallel with the first charge storage device.
1. A memory device, comprising:
a current selector component, including:
a first charge storage device having a first gate with a corresponding first threshold voltage, the first charge storage device configured to store a first charge; and
a second charge storage device coupled in parallel with the first charge storage device, the second charge storage device having a second gate with a corresponding second threshold voltage, distinct from the first threshold voltage, the second charge storage device configured to store a second charge; and
a magnetic memory component electrically coupled to the current selector component; and
control circuitry coupled to first gate and the second gate of the current selector component and configured to govern operation of the current selector component, including:
enabling a read operation on the magnetic memory component by selectively enabling the first charge storage device to cause the current selector component to supply a first current to the magnetic memory component, the first current corresponding to the first charge; and
enabling a write operation on the magnetic memory component by selectively enabling the first charge storage device and/or the second charge storage device to cause the current selector component to supply a second current, greater than the first current, to the magnetic memory component.
2. The memory device of claim 1 , wherein the first charge storage device comprises a transistor; and
wherein the first gate comprises a floating gate configured to store the first charge.
3. The memory device of claim 1 , wherein the first charge storage device comprises a transistor; and
wherein the first gate comprises a charge trap configured to store the first charge.
4. The memory device of claim 3 , wherein the first charge storage device is configured to:
store the first charge on a drain-side of the first gate; and
store a third charge on a source-side of the first gate.
5. The memory device of claim 1 , wherein a channel of the first charge storage device is electrically-insulated from a channel of the second charge storage device.
6. The memory device of claim 1 , wherein a channel doping of the first charge storage device is distinct from a channel doping of the second charge storage device.
7. The memory device of claim 1 , wherein a work function of the first charge storage device is distinct from a work function of the second charge storage device.
8. The memory device of claim 1 , further comprising a bitline; and
wherein a first terminal of the first charge storage device and a first terminal of the second charge storage device are each coupled to the bitline via the magnetic memory component.
9. The memory device of claim 1 , further comprising a source line; and
wherein a second terminal of the first charge storage device and a second terminal of the second charge storage device are each coupled to the source line.
10. The memory device of claim 1 , further comprising a first wordline and a second wordline; and
wherein the first gate is coupled to the first wordline and the second gate is coupled to the second wordline.
11. The memory device of claim 1 , wherein the first charge storage device comprises an N-channel device, a P-channel device, or a CMOS device.