IP Library Granted Patent US 10,614,867
Granted Patent B2
US 10,614,867 · App. 16/051,272 · Granted Apr 7, 2020

Patterning of high density small feature size pillar structures

Inventors: Gian Sharma (Fremont, CA); Amitay Levi (Cupertino, CA)
Assignee: SPIN MEMORY, INC.
G11C11/161G11C11/1659H01L43/08H01L43/10
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Quick Facts
Patent No.
US 10,614,867
App. No.
16/051,272
Granted
Apr 7, 2020
Kind
B2
Abstract

A method for forming an array of very small pillar structures having a very small feature size that is smaller than the resolution limit of photolithographic process available for patterning such structures. The method involves forming an array of silicon pillar structures over a layer of material that will ultimately form the pillar structures. The array of silicon pillar structures is repeatedly oxidized to form a layer of silicon oxide at an outer surface of the silicon pillar structures and then etched to remove the outer layer of oxide, thereby reducing the features size (i.e. diameter) of the silicon pillar structure. A final oxidation process entirely oxidizes the remaining silicon pillar structures, leaving an array of small silicon oxide pillar structures that can be used as a mask for patterning underlying layers, including the underlying pillar material. The process is especially useful for forming an array of magnetic memory pillars.

Claims (13)

1. A method for manufacturing an array of pillar structures, the method comprising:

depositing a pillar material over a substrate;

depositing a layer of silicon over the pillar material;

forming a mask structure over the layer of silicon, the mask structure including an array of patterned features;

performing material removal process to transfer the pattern of the mask structure onto the underlying layer of silicon to form an array of silicon pillar structures;

oxidizing the silicon pillar structures to form an outer oxide layer on the silicon pillar structure;

etching the silicon pillar structures to remove the oxide layer, thereby reducing the size of the silicon pillar structure; and

using the reduced size pillar structure as a mask to pattern the underlying pillar material.

2. The method as in claim 1 , wherein the processes of oxidizing the silicon pillar structures and performing an etching to remove the oxide layer is repeatedly performed until the final oxidation oxidizes the entire silicon pillar structure, leaving an array of silicon oxide structures.

3. The method as in claim 2 , using the array of silicon oxide structures as a mask to form the pillar material layer into an array of pillar structures.

4. The method as in claim 3 , wherein the array of pillar structures is formed by performing an etching process to remove portions of the pillar material.

5. The method as in claim 1 , wherein the pillar material comprises a plurality of layers arranged to form a magnetic memory element.

6. The method as in claim 1 , wherein the pillar material comprises a plurality of layers arranged to form a magnetic tunnel junction structure.

Assignments (4)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 11, 2021
From: SPIN (ASSIGNMENT FOR BENEFIT OF CREDITORS), LLC
To: INTEGRATED SILICON SOLUTION, (CAYMAN) INC.
Reel/Frame 057473/0319 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 20, 2021
From: SPIN MEMORY, INC.
To: SPIN (ASSIGNMENT FOR THE BENEFIT OF CREDITORS), LLC
Reel/Frame 056927/0038 →
CHANGE OF NAME Recorded Jan 9, 2019
From: SPIN TRANSFER TECHNOLOGIES, INC.
To: SPIN MEMORY, INC.
Reel/Frame 048040/0409 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 4, 2018
From: SHARMA, GIAN; LEVI, AMITAY
To: SPIN TRANSFER TECHNOLOGIES, INC.
Reel/Frame 047641/0997 →
Continuity (1)
Related Publication 20200043537A1 · Feb 6, 2020