Threshold voltage adjustment from oxygen vacancy by scavenge metal filling at gate cut (CT)
A method of controlling threshold voltage shift that includes forming a first set of channel semiconductor regions on a first portion of a substrate, and forming a second set of channel semiconductor regions on a second portion of the substrate. A gate structure is formed on the first set of channel semiconductor regions and the second set of channel, wherein the gate structure extends from a first portion of the substrate over an isolation region to a second portion of the substrate. A gate cut region is formed in the gate structure over the isolation region. An oxygen scavenging metal containing layer is formed on sidewalls of the gate cut region.
1. A method of controlling threshold voltage shift comprising:
forming a first set of channel semiconductor structures on a first portion of a substrate;
forming a second set of channel semiconductor structures on a second portion of the substrate;
forming a gate structure on the first set of channel semiconductor structures and the second set of channel semiconductor structures, wherein the gate structure extends from a first portion of the substrate over an isolation region to a second portion of the substrate;
forming a gate cut region is formed in the gate structure over the isolation region;
forming an oxygen scavenging metal containing layer on sidewalls of the gate cut region; and
forming a dielectric fill on the oxygen scavenging metal containing layer filling the gate cut region.
2. The method of claim 1 , wherein at least one of the first and second set of channel semiconductor structures comprises fin structures.
3. The method of claim 2 , wherein the n-type semiconductor devices are a first device type region of a substrate, and p-type semiconductor devices are in a second device type region of the substrate, wherein the oxygen scavenging metal containing layer is removed from the p-type semiconductor devices that are in the second device type region of the substrate.
4. The method of claim 1 , wherein at least one of the first and second set of channel semiconductor structures comprises nanosheets.
5. The method of claim 1 , wherein the gate structure comprises a gate dielectric and a work function metal gate conductor.
6. The method of claim 1 , wherein the oxygen scavenging metal containing layer is selected from the group consisting of titanium, aluminum, titanium aluminum, titanium aluminum carbon and combinations thereof.
7. The method of claim 1 , wherein the oxygen scavenging metal containing layer is deposited by atomic layer deposition.
8. The method of claim 1 , wherein the first and second set of channel semiconductor structures are components of n-type semiconductor devices.
9. The method of claim 1 , wherein the dielectric fill comprises silicon nitride.